Hynix Semiconductor Inc.

Skhynix Inc.

Seok Jin Joo

Min Kyu Lee

Hyung Seok Kim

Kyung Pil Hwang

Ju In Kim

Keum Hwan Noh

Sook Kyung Kim

Jong Hyun Wang

Jun Seop Chung

Seung Gu Ji

Eui Jin Kim

Yong Il Jung

A data storage apparatus includes a nonvolatile memory device including a plurality of memory blocks in which a plurality of word lines to which one or more pages are coupled are arranged, a data buffer configured to buffer data to be stored in the one or more pages of the nonvolatile memory device, and a processor configured to detect, when a sudden power off (SPO) occurs, one or more first pages in which an interference has occurred in a memory block in use and store data corresponding to the one or more first pages in which the interference has occurred among the data buffered in the data buffer in a backup memory block of the nonvolatile memory device.

Data storage apparatus and operating method thereof

Semiconductor memory device and method of operating same includes reading data stored in memory cells of a page; performing an error correction loop (ECC loop) including performing an error checking and correcting operation (ECC) on the read data; determining a number of bit errors in the read data; and when the number of bit errors is greater than a maximum number of correctable bits, incrementing the number of ECC iterations (ECC count) and increasing the maximum number of correctable bits; storing the ECC count until the number of bit errors is less than the maximum number of correctable bits; and programming corrected data to the memory cells when the stored ECC count is more than preset number.

Semiconductor memory device and method of operating the same

A method of operating a data storage device includes setting program verify voltages for verifying whether memory cells of a nonvolatile memory device are programmed to desired program states; transmitting the set program verify voltages to the nonvolatile memory device; generating data patterns respectively corresponding to program states based on the program verify voltages; transmitting a data pattern corresponding to the program verify voltages to the nonvolatile memory device; and programming the memory cells with the transmitted data pattern.

Data storage device and operating method thereof

A non-volatile memory device and a method for programming the same are disclosed. The non-volatile memory device includes first and second memory blocks, each of which includes a plurality of memory cells, each memory cell including a plurality of regions in which data is written, corresponding regions of the plurality of memory cells constituting a page; a data write unit, upon receiving a write signal and an address allocation signal, configured to write first data in a first page of the first memory block, and write second data in a first page of the second memory block; and a copy-back unit, upon receiving a chip idle signal and a copy-back control signal, configured to write the first data written in the first memory block into a second page of the second memory block.

Non-volatile memory device and method for programming the same

A program method of a semiconductor memory device includes performing a least significant bit (LSB) program operation for target LSB program cells of a selected page, increasing the threshold voltages of target most significant bit (MSB) program cells of the selected page before performing an MSB operation for the target MSB program cells, and performing the MSB program operation for the target MSB program cells after the increasing of the threshold voltages of the target MSB program cells.

Semiconductor memory device and method of programming the same

A semiconductor memory device includes a page buffer configured to store data read from a memory cell, a counter circuit configured to count the number of first data or second data in the read data for every read operation while the read operations are repeated a set number of times, and a control logic configured to determine the number of read operations and determine the read data of the memory cell based on the counted number.

Semiconductor memory device and operating method thereof

A method of operating a nonvolatile memory device comprises performing a read operation to read data stored in a first memory cell block including first unit groups; detecting a second unit group from among the first unit groups, the second unit group having a number of error bits included in the read data, which is greater than a set number of bits and equal to or smaller than a maximum allowable number of bits which can be corrected through an error checking and correction (ECC) processing; and after the second unit group is detected, performing a copyback operation for moving the data, that are stored in the first memory cell block, to a second memory cell block.

Nonvolatile memory device having a copy back operation and method of operating the same

In a method of performing a read operation of a nonvolatile memory device, a selected bit line is precharged. A pass voltage is sequentially applied to all word lines. The pass voltage applied to a word line, selected from among all the word lines, is changed for a read voltage. The read voltage is applied to the selected word line. Data of a memory cell coupled to the selected word line is read.

Method of performing read operation of nonvolatile memory device

According to a method of controlling the operation of a flash memory device including a number of memory blocks, a memory block of the memory blocks is first selected as a reference block. A program operation is performed on a memory cell included in the reference block. In order to check an operating characteristic of the reference block, a threshold voltage level of the programmed memory cell is read. Parameters for performing an operation of the flash memory device are determined based on the operating characteristic of the reference block. The parameters are stored in the reference block.

Method of controlling operation of flash memory device

A method of erasing and programming a flash memory device including multi-level cells (MLCs). MLCs of a word line are selected and some of the MLCs are pre-programmed based on whether their individual threshold voltages are included in a first voltage range. The selected MLCs are pre-programmed with a pre-program (first) voltage; and the remaining MLCs are prohibited from pre-programming; then the remaining MLCs connected to the selected word line are programmed by applying a program (second) voltage that gradually rises from the pre-program voltage at a ratio of a step voltage n for the selected line.

Program method of flash memory device

Erase and program methods of a flash memory device including MLCs for increasing the program speed. In the erase method, MLCs are pre-programmed so that a voltage range in which threshold voltages of MLCs are distributed can be reduced. Therefore, a fail occurrence ratio can be reduced when erasing MLCs, the threshold voltage distribution of MLCs can be improved and an overall program time can be shortened in a subsequent program operation.

Erase method of flash memory device

A read method of a memory device including a MLC includes the steps of performing a data read operation according to a first read command; determining whether error correction of the read data is possible; if, as a result of the determination, error correction is difficult, performing a data read operation according to a second read command; determining whether error correction of read data is possible according to the second read command; and if, as a result of the determination, error correction is difficult, performing a data read operation according to a N(N&#x2267;3, N is an integer) read command.

Read method of memory device

A nonvolatile memory device includes a first memory block including a plurality of memory cells provided between a first drain selection transistor and a source selection transistor; and a second memory block including a plurality of memory cells provided between a second drain selection transistor and the source selection transistor. The first and second memory blocks share the same source selection transistor that is supplied with a voltage via a source selection line.

Nonvolatile memory device and method of programming/reading the same

A method for programming a non-volatile memory device includes applying a first dummy voltage to a Multi-Level Cell (MLC). A first program voltage is applied to the MLC to program the MLC, the first program voltage being applied to the MLC after the first dummy voltage has been applied to the MLC. The MLC is verified whether or not the MLC has been programmed correctly by the first program voltage. A second dummy voltage is applied to the MLC after the first dummy voltage has been applied, the second dummy voltage being N volt higher than the first dummy voltage, wherein the second dummy voltage applied to the MLC is of sufficiently low voltage, so that the second dummy voltage does not change an initial state of the MLC. A third dummy voltage is applied to the MLC after the second dummy voltage has been applied, the third dummy voltage being N volt higher than the second dummy voltage.

Erase and program methods of a flash memory device including MLCs for increasing the program speed are described. In the erase method, MLCs are pre-programmed so that a voltage range in which threshold voltages of MLCs are distributed can be reduced. Therefore, a fail occurrence ratio can be reduced when erasing MLCs, the threshold voltage distribution of MLCs can be improved and an overall program time can be shortened in a subsequent program operation.

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Seoul, South Korea

Seok Jin Joo