Samsung Electronics Co., Ltd.

Seok-Jin Cho

Tae-Young Oh

Young-Hwa Kim

Kyung-Soo Ha

Jin-Hoon Jang

Jung-Hwan Park

Jin-Hun Jang

A semiconductor memory device includes a memory cell array and an address decoder. The memory cell array includes a plurality of memory blocks, each of the plurality of memory blocks includes a plurality of dynamic memory cells coupled to word-lines and bit-lines, each of the plurality of memory blocks are divided into a plurality of row blocks by row block identity bits of a row address, and each of the of row blocks includes a plurality of sub-array blocks arranged in a first direction. The address decoder changes a physical row address of a memory cell that stores or outputs data based on a column address received with a write command or a read command.

Semiconductor memory devices and methods of operating semiconductor memory devices

A memory device having a plurality of voltage regions and a method of operating the same are provided. The memory device includes a memory cell array, a data path region including data processing blocks transmitting read/write data from/to the memory cell array during read/write operations, and a control signal path region including control blocks controlling the data processing blocks during the read/write operations. The data path region selectively receives a first high power voltage or a first low power voltage in accordance with an operating mode of the memory device. The control signal path region receives the first high power voltage regardless of the operating mode.

Nonvolatile memory device and operating method of the same

A memory device has a plurality of power rails, including: a first power rail for transmitting a high power voltage, a second power rail for transmitting a low power voltage, a third power rail for selectively receiving the high power voltage from the first power rail through a first dynamic voltage and frequency scaling (DVFS) switch and for selectively receiving the low power voltage from the second power rail through a second DVFS switch, a fourth power rail connected to a first power gating (PG) switch to selectively receive the high power voltage or the low power voltage from the third power rail, and a first circuit block connected to the fourth power rail to receive a power voltage to which the DVFS and PG are applied. When power gating is applied, supply of the power voltage to the fourth power rail is blocked.

Memory device including a plurality of power rails and method of operating the same

An impedance calibration circuit includes a first code generator, a first code storing circuit, a second code generator and a second code storing circuit. The first code generator generates a pull-up control code obtained from a result of comparing a target output high level (VOH) voltage with a first voltage of a first node. The first code storing circuit stores the pull-up control code when the target VOH voltage becomes the same as the first voltage. The second code generator generates a pull-down control code obtained from a result of comparing the VOH voltage with a second voltage of a second node. The second storing circuit stores the pull-down control code when the target VOH voltage becomes the same as the second voltage. The first code storing circuit and the second code storing circuit store pull-up control code and pull-down control code pairs respectively.

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Seoul, South Korea

Seok-Jin Cho