Lx Semicon Co., Ltd.

Silicon Works Co., Ltd.

Seok Jae Oh

Jong Suk Lee

Young Bok Kim

Chung Hwan Son

Yeh Ju Ka

Won Hee Kim

Soo Yeun Lee

Disclosed are a clock phase converter and a phase converting method that can generate a converted clock signal with a desired amount of delay by selecting and outputting an output signal corresponding to a preset value among output signals of a plurality of delayed clock signal generators that detect the transition of a clock signal and generate delayed clock signals by sequentially delaying the clock signal by a certain period of time.

Clock phase converter and phase converting method

A clock data recovery circuit of a display suitable for recovering a clock from a clock data signal. The clock data recovery circuit includes a clock recovery circuit configured to delay an input clock through delay units of multiple stages, and output delayed clocks from the delay units, respectively; and a data recovery circuit configured to recover data of a clock data signal using a recovered clock selected among the delayed clocks.

Clock data recovery circuit of display and clock recovery circuit thereof

Disclosed herein is a method of controlling a display driving apparatus configured to operate a display device that displays an image. The method includes receiving a first image signal (RGB) from an external system, converting the first image signal (RGB) into a second image signal (RGB') in a format processable by a data driver, outputting the second image signal (RGB′), converting the second image signal (RGB′) into a source signal based on a data control signal generated by a timing controller, converting heat energy generated by the data driver into a voltage, calculating a temperature of the data driver based on the converted voltage, and changing a resistance for impedance matching between the timing controller and the data driver based on the calculated temperature.

Display driving apparatus for operating display device that displays image and control method therefor

The present disclosure discloses a clock and data recovery circuit. The clock and data recovery circuit may include a clock recovery unit configured to output a recovery clock signal by operating a first time-to-digital conversion circuit or a second time-to-digital conversion circuit depending on a phase difference between a clock of an input signal and the recovery clock signal, and a data recovery unit configured to sample data from the input signal and output recovery data.

Clock and data recovery circuit and source driver including the same

The present disclosure discloses a digital loop filter in an all-digital phase-locked loop. The digital loop filter may include a selection circuit configured to output one of a first data signal and a second data signal as valid data, a first operation circuit configured to output a first operation signal by adding or subtracting the valid data and a first register signal, a first register circuit configured to register the first operation signal and output the first operation signal as the first register signal, a second operation circuit configured to output a second operation signal by adding or subtracting a value of at least one bit of the valid data and the first register signal, and a second register circuit configured to store the second operation signal and output the second operation signal as a control signal.

Digital loop filter in all-digital phase-locked loop

The present disclosure discloses a time-to-digital conversion circuit for a clock and data recovery circuit. The time-to-digital conversion circuit may include a first time-to-digital conversion circuit enabled when a phase difference between a clock of an input signal and a recovery clock signal is greater than a reference phase difference and configured to output a first digital signal corresponding to the phase difference, and a second time-to-digital conversion circuit enabled when the phase difference is equal to or smaller than the reference phase difference and configured to output a second digital signal corresponding to the phase difference.

Time-to-digital conversion circuit and source driver including the same

The present disclosure discloses an all-digital phase-locked loop. The all-digital phase-locked loop may include a time-to-digital conversion circuit configured to convert phase differences between a reference signal and a feedback signal into respective digital values and to output a first data signal and a second data signal corresponding to the respective digital values, a digital loop filter configured to select one of the first data signal and the second data signal as valid data and output a control signal by operating the valid data and a first register signal, a digitally controlled oscillator configured to generate an oscillation signal and control a frequency of the oscillation signal in response to the control signal, and a divider configured to divide the oscillation signal and output the feedback signal to the time-to-digital conversion circuit.

Growing community of inventors

Daejeon, South Korea

Seok Jae Oh