Samsung Electronics Co., Ltd.

Seok-Hwan Oh

Jeong-Ho Yeo

Jin-seok Heo

Sang-Gyun Woo

Gi-Sung Yeo

Chang-min Park

Yool Kang

Sook Jin Lee

Cha-Won Koh

Seong-woon Choi

Doo-youl Lee

Sung-Gon Jung

Hyun-Jae Kang

Takahiro Yasue

Joo-On Park

So-Ra Han

Dae-Joung Kim

Seong-Ho Moon

Subramanya Mayya

Jin-Seok Heo

Hyoung-hee Kim

Jang-Ho Shin

A method of manufacturing a mask includes dividing an upper surface of a template having a design pattern into a plurality of regions, the template being arranged over a polymer layer on a mask substrate, correcting a distorted region among the regions, pressing the polymer layer with the template to form a mask pattern corresponding to the design pattern on the polymer layer; and curing the mask pattern.

Method of manufacturing a mask

Apparatus for manufacturing a mask

A method of measuring an overlay of an object is provided. In the method, first information of a first structure may be obtained. A preliminary structure may be formed on the first structure. Second information of the preliminary structure may be obtained. The first information and the second information may be processed to obtain virtual information of a second structure that would be formed on the first structure if a process is performed on the preliminary structure. A virtual overlay between the first structure and the second structure may be measured using the virtual information.

Method of measuring an overlay of an object

Methods of forming photoresist patterns may include forming a photoresist layer on a substrate, exposing the photoresist layer using an exposure mask, forming a preliminary pattern by developing the exposed photoresist layer and treating a surface of the preliminary pattern using a treatment agent that includes a coating polymer.

Methods of forming photoresist patterns

The energy distribution of exposure light directed passing through the slit of an exposure apparatus is determined. A photoresist layer on a substrate is exposed over a plurality of shots while changing the intensity of the exposure light for each shot. Then the photoresist layer is developed to form a sample photoresist layer. An image of the developed sample photoresist layer is analyzed for color intensity. Values of the color intensity across a selected one of the shots are correlated with values of the intensity of the exposure light to produce an energy distribution of the exposure light along the length of the slit. The energy distribution is used to change the slit so that a more desirable energy distribution may be realized when the slit is used in a process of manufacturing a semiconductor device.

Photolithography method including technique of determining distribution of energy of exposure light passing through slit of exposure apparatus

A method of forming a mask pattern, a method of forming a minute pattern, and a method of manufacturing a semiconductor device using the same, the method of forming the mask pattern including forming first mask patterns on a substrate; forming first preliminary capping layers on the first mask patterns; irradiating energy to the first preliminary capping patterns to form second preliminary capping layers ionically bonded with the first mask patterns; applying an acid to the second preliminary capping layers to form capping layers; forming a second mask layer between the capping layers, the second mask layer having a solubility lower than that of the capping layers; and removing the capping layers to form second mask patterns.

Method of forming a mask pattern, method of forming a minute pattern, and method of manufacturing a semiconductor device using the same

Mask sets are provided which may be used to define a first pattern region that has a first pitch pattern and a second pattern region that has a second pitch pattern during the fabrication of a semiconductor device. These mask sets may include a first mask that has a first exposure region in which a first halftone pattern defines the first pattern region and a first screen region in which a first shield layer covers the second pattern region. These mask sets may further include a second mask that has a second exposure region in which a second halftone pattern defines the second pattern region and a second screen region in which a second shield layer covers the first pattern region. The second shield layer also extends from the second screen region to cover a portion of the second halftone pattern.

Multi-exposure semiconductor fabrication mask sets and methods of fabricating such multi-exposure mask sets

There are provided a semiconductor device having an overlay measurement mark, and a method of fabricating the same. The semiconductor device includes a scribe line region disposed on a semiconductor substrate. A first main scale layer having a first group of line and space patterns and a second group of line and space patterns is disposed on the scribe line region. Line-shaped second main scale patterns are disposed on space regions of the first group of the line and space patterns. Line-shaped vernier scale patterns are disposed on space regions of the second group of the line and space patterns. In the method, a first main scale layer having a first group of line and space patterns and a second group of line and space patterns is formed on a semiconductor substrate. Line-shaped second main scale patterns are formed on space regions of the first group of the line and space patterns. Line-shaped vernier scale patterns are formed on space regions of the second group of the line and space patterns.

Semiconductor device having overlay measurement mark and method of fabricating the same

A method of detecting measurement errors in a measurement system includes: a) imaging a pattern, the imaged pattern including a plurality of critical dimension measurement dots, and b) automatically detecting a non-smooth connection of the plurality of the critical dimension measurement dots.

Method of detecting measurement error in measurement system

In a method for forming a semiconductor device and a semiconductor device having an overlay mark, a first pattern for the semiconductor device is formed in a semiconductor device formation region of a semiconductor substrate and simultaneously in a first mark formation region of the semiconductor substrate. A second pattern for the semiconductor device is formed on a resultant structure in the semiconductor device formation region of the semiconductor substrate and simultaneously in a second mark formation region of the semiconductor substrate. The first and second patterns in the first and second mark formation regions, respectively, are inspected for misalignments using overlay marks formed to have shapes and sizes identical to those of real patterns in the semiconductor device formation region of the semiconductor substrate. By measuring misalignments of real patterns using the overlay marks, overlay mismatch between the semiconductor device formation region and the overlay mark may be prevented.

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Seoul, South Korea

Seok-Hwan Oh