Samsung Electronics Co., Ltd.

Seok Ho Kim

Kwang Jin Moon

Ho Jin Lee

Byung Lyul Park

Hoon Joo Na

Nae In Lee

Tae Yeong Kim

Jong Rip Lee

Sung Hyun Lee

Jae Hyung Park

Hyung Jun Jeon

Kyu Ha Lee

Chi-sung Oh

Ju Bin Seo

Seock Woo Jang

Sung Hwa Lee

Hoe Chul Kim

Joo Hee Jang

Hyug Rae Cho

Pil Kyu Kang

A semiconductor package that include first and second semiconductor chips bonded together, wherein the first semiconductor chip includes a first semiconductor substrate, a first semiconductor element layer and a first wiring structure sequentially stacked on a first surface of the first semiconductor substrate, first connecting pads and first test pads on the first wiring structure, and first front-side bonding pads, which are connected to the first connecting pads, wherein the second semiconductor chip includes a second semiconductor substrate, a second semiconductor element layer and a second wiring structure sequentially stacked on a third surface of the second semiconductor substrate, and first back-side bonding pads bonded to the first front-side bonding pads on the fourth surface of the second semiconductor substrate, and wherein the first test pads are not electrically connected to the second semiconductor chip.

Semiconductor package and method of fabricating the same

A wafer bonding apparatus is provided includes a lower support plate configured to structurally support a first wafer on an upper surface of the lower support plate; a lower structure adjacent to the lower support plate and movable in a vertical direction that is perpendicular to the upper surface of the lower support plate, an upper support plate configured to structurally support a second wafer on a lower surface of the lower support plate, and an upper structure adjacent to the upper support plate and movable in the vertical direction.

Wafer bonding apparatuses

A method for wafer planarization includes forming a second insulating layer and a polishing layer on a substrate having a chip region and a scribe lane region; forming a first through-hole in the polishing layer in the chip region and the scribe lane region and a second through-hole in the second insulating layer in the chip region, wherein the second through-hole and the first through-hole meet in the chip region; forming a pad metal layer inside the first through-hole and the second through-hole and on an upper surface of the polishing layer; and polishing the polishing layer and the pad metal layer by a chemical mechanical polishing (CMP) process to expose an upper surface of the second insulating layer in the chip region and the scribe lane region.

Method for wafer planarization and an image sensor made by the same

There is provided a method for fabricating a substrate structure capable of enhancing process reproducibility and process stability by trimming a bevel region of a substrate using a wafer level process. The method includes providing a first substrate including first and second surfaces opposite each other and a first device region formed at the first surface, providing a second substrate including third and fourth surfaces opposite each other and a second device region at the third surface, bonding the first substrate and the second substrate to electrically connect the first device region and the second device region, and forming a trimmed substrate. The forming the trimmed substrate includes etching an edge region of the second substrate bonded to the first substrate.

Method for fabricating substrate structure and substrate structure fabricated by using the method

A method of manufacturing a substrate structure includes providing a first substrate including a first device region on a first surface, providing a second substrate including a second device region on a second surface, such that a width of the first device region is greater than a width of the second device region, and bonding the first substrate and the second substrate, such that the first and second device regions are facing each other and are electrically connected to each other.

Method of manufacturing substrate structure

A semiconductor memory package includes a base layer that communicates with a memory controller; at least one memory layer that is stacked on the base layer; and at least one through silicon via that penetrates through the at least one memory layer, wherein at least one signal bump for exchanging a signal with the memory controller is disposed in a first area of the base layer located to be adjacent to the memory controller, and wherein the first area corresponds to an edge area of the base layer, and a power bump for receiving power from outside of the semiconductor memory package for performing a signal processing operation on the signal is disposed in a second area of the base layer contacting the at least one through silicon via, wherein the second area corresponds to an area other than edge areas of the base layer.

Semiconductor memory package including stacked layers and memory device and semiconductor memory system having the same

Assigning identifiers to a plurality of test devices to manage the test devices, and displaying the assigned identifiers on the test devices to distinguish the test devices.

Management system of test device and management method thereof

A method and apparatus for controlling driving of a test device that analyzes a sample are provided. The method includes identifying a test device, executing a script containing a plurality of operations to be performed to analyze the sample contained in the test device, wherein the script includes a plurality of operation commands, wherein at least one operation command among the plurality of operation commands includes a conditional statement, and wherein at least one operation command among the plurality of operation commands is designated to be executed according to whether the conditional statement is satisfied.

Growing community of inventors

Hwaseong-si, South Korea

Seok Ho Kim