Samsung Electronics Co., Ltd.

Seok-Han Park

Joo-Sung Park

Bum-seok Seo

Dong-Hyun Han

Jeong-seop Shim

A method of forming an isolation structure, wherein a hard mask is formed on a first region and a second region of a substrate; the substrate is etched using the hard mask as an etching mask to form a plurality of first active patterns in the first region and a plurality of second active patterns in the second region, a first trench between the first active patterns having a first trench width, and a second trench between the second active patterns having a second trench width smaller than the first trench width; a first oxide layer is formed on the hard mask and the first and second trenches; the first oxide layer is conformally formed on an inner wall of the first trench and filling the second trench; a polysilicon layer is conformally formed on the first oxide layer and a spin-on-dielectric (SOD) layer is formed on the polysilicon layer to fill the first trench; and the SOD layer and the polysilicon layer are annealed using an oxygen-containing gas so that the SOD layer and the polysilicon layer are transformed into a second oxide layer and a third oxide layer, respectively, in the first trench, resulting in a semiconductor device with an isolation structure with good isolation characteristics.

Methods of forming an isolation structure and methods of manufacturing a semiconductor device including the same

Provided is a method of forming fine patterns, which is capable of easily forming a plurality of patterns repeatedly with a fine pitch when forming patterns necessary for manufacturing a highly integrated semiconductor device exceeding a resolution limit of a photolithography process.

Method of forming fine patterns

In a method of forming patterns of a semiconductor device, an object layer is formed on a substrate. A plurality of guiding pillars and at least one guiding dam are formed on the object layer. A self-aligned layer including a block copolymer is formed in a space between the guiding pillars and the guiding dam, such that first blocks aligned around the guiding pillars and second blocks aligned around the guiding dam are formed. A trim pattern at least partially covering the guiding dam is formed. The first blocks are transferred in the object layer.

Methods of forming patterns of semiconductor devices

A method of forming a pattern including forming a feature layer on a substrate having first and second regions; forming a first guide pattern on the first region, the first guide pattern having openings therein, the openings exposing the feature layer; forming a second guide pattern covering the feature layer exposed through the first guide pattern on the first region and covering the second region; forming a block copolymer layer covering the first guide pattern and the second guide pattern on the first and second regions; phase-separating the block copolymer layer to form first vertical domains and a second vertical domain; removing the first vertical domains on the first region; and etching the first guide pattern and the feature layer using the second vertical domain as an etch mask on the first region to form a feature pattern having holes therein.

Method of forming pattern and method of manufacturing integrated circuit device by using the same

A method of manufacturing a semiconductor device comprising the steps of: forming a trench at an upper portion of a semiconductor substrate forming a preliminary filling insulation layer by coating a siloxane composition on the semiconductor substrate to fill the trench performing a low temperature curing process at a temperature in a range from about 50&#xb0; C. to about 150&#xb0; C. such that the preliminary filling insulation layer is transformed into a filling insulation layer including polysiloxane and forming an isolation layer by planarizing the filling insulation layer.

Methods of manufacturing semiconductor devices including isolation layers

A method of forming a pattern, the method including forming a mask layer on a feature layer on a substrate; forming guides regularly arranged with a first pitch on the mask layer in a first region and dummy guides regularly arranged with the first pitch on the mask layer in a second region spaced apart from the first region with a separation region therebetween, the separation region having a width greater than the first pitch; forming a block copolymer layer on the mask layer; phase-separating the block copolymer layer to form a self-assembled layer; forming a mask pattern by etching the mask layer using the self-assembled layer; and patterning the feature layer by transferring a shape of the mask pattern to the feature layer in the first region while blocking the shape of the mask pattern from being transferred to the feature layer in the second region.

An alignment key structure in a semiconductor device is provided. The alignment key structure includes an insulation layer formed on a substrate, and a passivation layer pattern formed on the insulation layer. The insulation layer includes a plurality of metal wirings. The passivation layer pattern includes a first opening that exposes at least one of the metal wirings. Moreover, the first opening has a width which is narrower than a width of the exposed metal wiring.

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Hwaseong-si, South Korea

Seok-Han Park