Samsung Electronics Co., Ltd.

Seok-Cheon Kwon

Young-Joon Choi

Kyeong-Han Lee

Jong-Hwa Kim

Jae Young Lee

Dong-Yang Lee

Seok-heon Lee

Dong-hwan Kim

Gwang-Man Lim

Seok-Jae Han

Il-Mok Kang

In-Young Kim

Yeon-Ho Kim

Hyung-Gon Kim

Seok-Chan Lee

Tae-Hee Cho

Sang-Chul Kang

Jae-Young 102-803 Jugong 1 Dani Lee

A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.

Nonvolatile memory device including a peripheral circuit to receive an address in synch with one of a rising and falling edge of a signal regardless of whether a first or second alignment type is selected and nonvolatile memory system including the same

Flash memory device and flash memory system including the same

A flash memory device includes a memory cell array, a clock signal input, an input for receiving a signal designating a writing operating mode, a plurality of data input/output pads, and a data input/output buffer circuit that is electrically connected to the clock signal input and to the plurality of data input/output pads. The data input/output buffer circuit is configured to receive data that is to be written to the memory cell array through the data input/output pads in synchronization with a clock signal that is applied to the clock signal input in response to activation of the signal designating the writing operating mode.

Flash memory devices with high data transmission rates and memory systems including such flash memory devices

A system and method are provided for booting a computing device using a NAND flash memory. Boot code stored in the NAND flash memory is transferred to a RAM for execution by the CPU. Operating system program stored in the NAND flash memory is transferred to a system memory for execution therefrom by the CPU after system boot.

System boot using NAND flash memory and method thereof

A nonvolatile semiconductor memory device comprises an address buffer, a column address register, a selection circuit, a data input/output circuit, and a controller. The controller controls the column address changes of the memory device during the read/write operation. When external addresses are applied to a first input/output pins while data is transferred from a second input/output pins to an internal register or is transferred from the internal register to the second input/output pins through the data input/output circuit, the control circuit stores the external addresses in the column address register as a column address. A page size of the nonvolatile semiconductor memory device having such a column address change function can be increased irrespective of a memory system.

Nonvolatile semiconductor memory device and data input/output control method thereof

A semiconductor memory device has at least one data line, registers for storing data bits, and switch elements corresponding to the registers for transferring the data bits to the data line in response to corresponding selection signals. It also has a precharge circuit connected to the data line, for precharging the data line to a power supply voltage in response to a precharge control signal. The selection signals are sequentially activated at a predetermined time interval by synchronously responding to a clock signal, and the precharge control signal is activated during the interval of the selection signals, by synchronously responding to the clock signal.

Data line precharging circuit of a semiconductor memory device

A nonvolatile semiconductor memory device of the present invention has an array that includes a bit line, a plurality of word lines arranged perpendicularly to the bit line and a plurality of memory cells each arranged at intersections of the bit line and the word lines. In the nonvolatile semiconductor memory device is further provided a storage circuit and a program data judging circuit. The storage circuit has at least two latches each of which is connected to a corresponding input/output line and latches data. The program data judging circuit judges whether logic states of data latched in the latches indicate a programming or a program-inhibition of a selected memory cell, and sets the bit line to a program voltage or a program inhibition voltage according to a judgment result.

Multi-state nonvolatile semiconductor memory device which is capable of regularly maintaining a margin between threshold voltage distributions

A nonvolatile semiconductor memory device includes a memory cell array divided into a plurality of memory blocks. A plurality of bit lines are arranged through the plurality of memory blocks, and a plurality of word lines are arranged in each of the memory blocks so as to intersect the bit lines. Each of the memory blocks includes a plurality of memory cell strings corresponding to the bit lines. Each memory cell string includes a first string segment having a plurality of EEPROM cells and a second string segment having a plurality of EEPROM cells. A first select transistor connects the first string segment to a corresponding bit line in response to a first select signal. A second select transistor connects the first string segment to the second string segment in response to a second select signal. And a third select transistor connects the second string segment to a common source line in response to a third select signal.

Memory cell string structure of a flash memory device

A nonvolatile semiconductor memory device includes a program state detection circuit for checking a state of programmed memory cells. The program state detection circuit checks program pass/fail using data transmitted through a column selection circuit, according to a column address having redundancy information. Therefore, it is possible to overcome the problem that the memory device is regarded as a fail device owing to a defective column.

Flash memory device with program status detection circuitry and the method thereof

A nonvolatile semiconductor memory device has a memory block including a string having a string select transistor responsive to a string select line, a ground select transistor responsive to a ground select line, and a plurality of EEPROM cells responsive to a corresponding plurality of word lines, the plurality of EEPROM cells being serially connected between the string select transistor and the ground select transistor. A first block select transistor is coupled to the ground select transistor. A second block select transistor is coupled to the string select transistor. A plurality of third block select transistors is coupled to the plurality of word lines. A voltage control means provides a first voltage to the first block select transistor and a second voltage to the third block select transistors, the first voltage being less than the second voltage during programming. According to the present invention, a voltage difference occurring between the gate and the drain of the first block select transistor is reduced. The result is a significant stress reduction on the first block select transistor.

Growing community of inventors

Gyeonggi-do, South Korea

Seok-Cheon Kwon