Mediatek Singapore Pte. Ltd.

Mediatek Corporation

Senthilkumar Jayapal

Yipin Wu

Chaoqun Liu

Navienkumar Ramachandran Arumugam

Chih-Hung Tai

Soh Chee Keong

Yang Bai

A droop reduction circuit on a die includes a voltage detector circuit to detect voltage droop in a supply voltage received by a first load. The droop reduction circuit further includes a driver controller circuit to drive power switch (PSH) banks in response to detection of the voltage droop. Each of the PSH banks includes at least one power switch having an input terminal, a gate terminal, and an output terminal. The input terminal is to receive a secondary voltage, which is higher than the supply voltage and is also received by a second load on the die. The gate terminal is to receive a drive signal from the driver controller, and the output terminal is to pull up the voltage droop in the supply voltage.

Voltage droop reduction with a secondary power supply

A device for reducing leakage current includes a memory cell array, a power switch and a core logic. The memory cell array is electrically connected to a first power rail which supplies a first voltage level. The core logic circuitry is electrically connected to a second power rail via the power switch when the power switch is turned on. The second power rail supplies a second voltage level which is lower than the first voltage level. The power switch is to be turned off by the first voltage level supplied to a gate terminal of the power switch, to thereby disconnect the core logic circuitry in a sleep state from the second power rail.

Leakage current reduction in a dual rail device

Examples of multi-voltage (MV) complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) based on always-on N-well architecture are described. A MV CMOS IC may include first CMOS cells, second CMOS cells, N-wells and always-on taps. Each first CMOS cell may have a supply terminal configured to receive a local supply voltage, and an N-well (NW) terminal configured to receive a global supply voltage. The second CMOS cells may include always-on CMOS cells. Each second CMOS cell may have a supply terminal configured to receive the global supply voltage, and an NW terminal configured to receive the global supply voltage. The NW terminal of at least one of the second CMOS cells and the NW terminal of at least one of the first CMOS cells may be formed in a first N-well of the one or more N-wells.

Multi-voltage complementary metal oxide semiconductor integrated circuits based on always-on N-well architecture

A retention mode sequential logic circuit has no balloon latch, and all its P-channel transistors are disposed in a single N-well. In one example, the circuit is a retention flip-flop that has an active high retention signal input and an active low reset input. In another example, the circuit is a retention flip-flop that has an active low retention signal input and an active low reset input. In a multi-bit retention register example, one common clock and reset signal generation logic circuit drives multiple pairs of latches. Each retention mode logic circuit described has a low transistor count, is implemented with a single N-well, exhibits low retention mode power consumption, is not responsive to a reset signal in the retention mode, and has a fast response time when coming out of retention mode operation.

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Singapore, Singapore

Senthilkumar Jayapal