Oracle International Corporation

Toshiba Memory Corporation

Senthilkumar Diraviam

Ali Vahidsafa

Sebastian Turullols

David Malcolm Symons

Paul Edward Hanham

Mark Semmelmeyer

Francesco Giorgio

Scott Cooke

Alan Smith

Jonghyeon Kim

Yibin Xia

Mohd Jamil Mohd

Preethi Sama

Dinesh Rajasavari Amirtharaj

Various implementations described herein relate to systems and methods for correcting data from memory systems such as a plurality of non-volatile memory devices of a Solid State Drive (SSD), including but not limited to, receiving frames of the data from the plurality of non-volatile memory devices, allocating the frames among pooled frontline Error Correction Code (ECC) decoders, decoding, by the pooled frontline ECC decoders, the frames to output first decoded frames, and returning the first decoded frames to the read channels.

Pooled frontline ECC decoders in memory systems

Embodiments include systems and methods for in-system, scan-based device testing using novel narrow-parallel (NarPar) implementations. Embodiments include a virtual automated test environment (VATE) system that can be disposed within the operating environment of an integrated circuit for which scan-based testing is desired (e.g., a chip under test, or CuT). For example, the VATE system is coupled with a service processor and with the CuT via a novel NarPar interface. A sequence controller can drive a narrow set of parallel scan pins on the CuT via the NarPar interface of the VATE system in accordance with an adapted test sequence having bit vector stimulants and expected responses. Responses of the CuT to the bit vector stimulants can be read out and compared to the expected results for scan-based testing of the chip.

Narrow-parallel scan-based device testing

Systems, methods, and other embodiments associated with providing a unified tool for performing design constraints generation and verification for circuit designs are described. In one embodiment, the unified tool reads design data and design intent information for a circuit design. The unified tool generates physical flow elements and verification flow elements of the circuit design, together and in dependence on each other, based, at least in part, on the design data and the design intent information.

Unified tool for automatic design constraints generation and verification

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Sunnyvale, CA, United States of America

Senthilkumar Diraviam