Texas Instruments Corporation

Senthil Kumar Sundaramoorthy

Uming U Ko

Clive D Bittlestone

Dharin Nayeshbhai Shah

Timothy Alan Rost

Sumanth Katte Gururajarao

Rolf Lagerquist

Girishankar Gurumurthy

Cynthia Ann Torres

Rakesh Dimri

Victor James Nuss

A device comprising a semiconductor substrate. The device also comprising a digital block defined on the substrate and having multiple electronic elements. The device also comprises first and second poly layers coupling to the multiple electronic elements, the first and second poly layers extending in parallel through the digital block in a first direction. The device further comprising a third poly layer coupled to the first poly layer and extending through a gap in the second poly layer in a second direction orthogonal to the first direction poly.

Digital blocks with electrically insulated and orthogonal polysilicon layers

An electrostatic discharge (ESD)-triggered protection apparatus includes a first circuit and a second circuit. The first circuit includes an ESD trigger circuit to sense an ESD pulse and to generate a switching pulse responsive to the ESD pulse; a first ESD discharge device communicatively coupled to the ESD trigger circuit and responsive to the switching pulse to transfer a current generated by the ESD pulse to the ground rail; a control circuit that generates a control signal in response to the switching pulse. The second circuit includes at least one trigger cell buffer that is configured to receive the control signal and to control a second ESD discharge device such that the current generated by the ESD pulse is transferred to the ground rail.

Electrostatic discharge protection apparatus

An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at least two rows and comprises a PMOS transistor having a source/drain region that spans across one of the row boundaries and an NMOS transistor having a source/drain region that spans across one of the row boundaries.

Performance and area scalable cell architecture technology

Growing community of inventors

Bengaluru, India

Senthil Kumar Sundaramoorthy