International Business Machines Corporation

Senthil K Srinivasan

Ravikumar Ramachandran

Chandrasekhar Narayan

Richard Anthony Conti

Chienfan Yu

Rebecca D Mih

Joyce C Liu

Axel Christoph Brintzinger

John W Golz

Donna Rizzone Cote

Thomas S Rupp

Jin J Wu

Kenneth C Arndt

Teresa Jacqueline Wu

Jeffrey J Brown

George A Kaplita

James C Brighten

A method for fabricating a dual gate structure, comprising providing a semiconductor substrate having a first device area and a second device area covered by a gate oxide layer and a polysilicon layer, forming a first hard mask over the polysilicon layer, said first hard mask being a material that is resistant to a first etching, but susceptible to a second etching forming a second hard mask over the first hard mask and the polysilicon layer, said second hard mask being a material that is resistant to a second etching, but susceptible to a first etching, patterning and etching said second hard mask with a first etch to form a gate pattern on a first device area, and patterning and etching said first hard mask with a second etch to transfer gate patterns on the first and second device areas.

Dual mask process for semiconductor devices

A structure and method for making a cavity fuse over a gate conductor stack. The method includes providing a semiconductor substrate having a gate conductor stack over a shallow trench isolation region, forming oxide layers on the substrate about the gate conductor stack, etching electrical contact holes through the oxide layers to the substrate, filling the electrical contact holes with a first conductive material to establish electrical contact with the gate conductor stack, etching a pattern in an uppermost oxide layer of the oxide layers, depositing a conductive layer of a second conductive material over the oxide layers and the electrical contacts, planarizing the conductive layer whereby the conductive material remains only in the pattern, anisotropically etching the oxide layers to form at least one etching hole through the oxide layers to the shallow trench isolation region, and isotropically etching at least a portion of the oxide layers about the etching hole, whereby a cavity is formed beneath at least a portion of the conductive layer pattern, the gate conductor stack comprising a fuse.

Manufacturing of cavity fuses on gate conductor level

Growing community of inventors

Wappingers Falls, NY, United States of America

Senthil K Srinivasan