Lsi Logic Corporation

Sengsooi Lim

Ramaswamy Ranganathan

Qwai Hoong Low

Sunil A Patel

An improved tape substrate design for a semiconductor package is disclosed. The tape substrate semiconductor package includes a plurality of die pads, a plurality of vias, and a pattern of metal traces interconnected between the die pads and the vias to form circuitry on the tape substrate. According to the method and apparatus of the present invention an extra metal layer is added at the circuitry to increase rigidity of the tape substrate, thereby reducing warpage without adding to the thickness of the tape substrate package.

Tape design to reduce warpage

The subject method comprises providing a semiconductor package and a semiconductor package substrate having respective first and second major sides. A stiffener member, which is attachable to the semiconductor package substrate, is employed for purposes of minimizing package warpage. The stiffener member is attached to the semiconductor package substrate to provide the requisite support for the semiconductor package substrate during the assembly process and thereby counteract the sources of the package warpage problem. A protective outer layer can be optionally added to the subject system.

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San Jose, CA, United States of America

Sengsooi Lim