Micron Technology Incorporated

Seng Kim Ye

Hong Wan Ng

Chin Hui Chong

Kelvin Tan Aik Boo

Hem P Takiar

See Hiong Leow

Ling Pan

Kelvin Aik Boo Tan

Chye Lin Toh

Peng Wang Low

Leng Cher Kuah

Methods, systems, and devices for wire bonding for stacked memory dies are described. A memory system may include a stack of memory dies. As the stack grows to include more and more memory dies, the length of the wires coupling the memory dies with the control circuit may increase. Bonding multiple wires using an adhesive may increase a gap between neighboring wires coupled with the same memory die or different memory dies. For example, bonding one wire to a neighboring wire may pull one or both of the bonded wires away from their original placement, increasing a gap between the bonded wires and one or more neighboring wires. Bonding the wires coupled with a lower memory die may increase a gap such that sagging wires coupled with an upper memory die may be positioned in the gap to avoid shorting with the lower wires.

Wire bonding for stacked memory dies

Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly includes a first semiconductor die, a second semiconductor die in a stacked arrangement with the first semiconductor die, and a flexible interposer disposed between the first semiconductor die and the second semiconductor die. The flexible interposer may include a first flexible layer, a second flexible layer, and a conductive trace disposed between the first flexible layer and the second flexible layer. A spacer portion of the flexible interposer may space the first semiconductor die from the second semiconductor die. A connecting portion of the flexible interposer may extend from the spacer portion beyond edges of the first semiconductor die and the second semiconductor die.

Flexible interposer for semiconductor dies

An apparatus includes a primary layer of a substrate. The apparatus includes a secondary layer of the substrate having a first open area that extends through the secondary layer to an inner layer of the substrate. The apparatus includes the inner layer of the substrate that is positioned between the primary layer and the secondary layer. The inner layer includes first component bond pads that are disposed on the inner layer and that are exposed via the first open area of the secondary layer.

Surface mount device bonded to an inner layer of a multi-layer substrate

Semiconductor devices with three-dimensional trace matching features, and related systems and methods, are disclosed herein. In some embodiments, an exemplary semiconductor device includes at least one semiconductor die and a redistribution layer disposed over the at least one semiconductor die and extending across a longitudinal plane. The redistribution layer includes first and second traces each electrically coupled to the at least one semiconductor die. The first trace is disposed in a first travel path included in a first effective path length. The second trace is disposed in a second travel path different from the first travel path. The second the second travel path includes at least one segment at a non-right, non-zero angle such that the at least one segment is neither parallel nor perpendicular to the longitudinal plane. Further, the second travel path is included in a second effective path length equal to the first path length.

Three dimensional semiconductor trace length matching and associated systems and methods

A semiconductor device assembly including a substrate; a first split via including a first via land that is disposed on a surface of the substrate and that has a first footprint with a half-moon shape with a first radius of curvature, and a first via that passes through the substrate and that has a second radius of curvature, wherein the first via is disposed within the first footprint; and a second split via including a second via land that is disposed on the surface of the substrate and that has a second footprint with the half-moon shape with the first radius of curvature, and a second via that passes through the substrate and that has the second radius of curvature, wherein the second via is disposed within the second footprint, wherein the first and second via lands are disposed entirely within a circular region having the first radius of curvature.

Split via structure for semiconductor device packaging

Semiconductor devices including thermally conductive structures are disclosed herein. A heat transfer structure may be thermally coupled to a semiconductor device and directly attached to a signaling layer of a substrate. The heat transfer structure may be configured to remove thermal energy from the semiconductor device and transfer at least a portion of the removed thermal energy directly into the signaling layer for dissipation within the substrate, for transfer through the substrate and out of a corresponding apparatus, or a combination thereof.

Apparatus including direct-contact heat paths and methods of manufacturing the same

A semiconductor package having a package substrate including an upper surface, a controller, a first die stack, and a second die stack. The controller, the first die stack, and the second die stack are at the upper surface. The first die stack includes a first shingled sub-stack and a first reverse-shingled sub-stack. The first die stack also includes a first bridging chip between the first shingled and reverse-shingled sub-stacks. The second die stack similarly includes a second shingled sub-stack and a second reverse-shingled sub-stack. The second die stack also includes a second bridging chip bonded to the top of the second reverse-shingled sub-stack. At least a portion of a bottom semiconductor die of the first reverse-shingled sub-stack is vertically aligned with a semiconductor die of the second shingled sub-stack and a semiconductor die of the second reverse-shingled sub-stack.

Cross stack bridge bonding devices and associated methods

A semiconductor device assembly is provided. The assembly includes a substrate having an upper surface on which is disposed a first device contact, a keep-out region extending from a first side surface of the substrate to a second side surface of the substrate opposite the first, and at least one trace coupled to the first device contact and extending across the keep out region towards a third side surface of the substrate. The assembly further includes at least one semiconductor device disposed over the upper surface of the substrate and coupled to the first device contact. The keep-out region of the substrate is free from conductive structures other than the at least one trace.

Multi-role semiconductor device substrates, semiconductor device assemblies employing the same, and methods for forming the same

A semiconductor device includes a rigid flex circuit that has a first rigid region and a second rigid region that are electrically connected by a flexible portion. A first die is mounted to a first side of the first rigid region. A second die is mounted to a second side of the second rigid region. The first and second sides are on opposite sides of the rigid flex circuit. The flexible portion is bent to hold the first and second rigid regions in generally vertical alignment with each other.

Semiconductor assemblies with systems and methods for managing high die stack structures

Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to corresponding to first and second distances between electrical contacts of the first and second surface-mount capacitors.

Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods

A semiconductor package including a package substrate with an upper surface, a controller, and a die stack. The controller and the die stack are at the upper surface. The die stack includes a shingled sub-stack of semiconductor dies, a reverse-shingled sub-stack of semiconductor dies, and a bridging chip. The bridging chip is bonded between the shingled sub-stack and the reverse-shingled sub-stack, and has an internal trace. A first wire segment is bonded between the controller and a first end of the bridging chip, and a second wire segment is bonded between a second end of the bridging chip and each semiconductor die of the shingled sub-stack. The internal trace electrically couples the first and second wire segments. Additionally, a third wire segment is bonded between the controller and each semiconductor die of the reverse-shingled sub-stack.

Through stack bridge bonding devices and associated methods

Semiconductor devices having three-dimensional bonding schemes and associated systems and methods are disclosed herein. In some embodiments, the semiconductor device includes a package substrate, a stack of semiconductor dies carried by the package substrate, and an interconnect module carried by the package substrate adjacent the stack of semiconductor dies. The stack of semiconductor dies can include a first die carried by the package substrate and a second die carried by the first die. Meanwhile, the interconnect module can include at least a first tier and a second tier. The first tier can be carried by and electrically coupled to the package substrate, and the second tier can be carried by and electrically coupled to the first tier. In turn, the second die can be electrically coupled to the second tier.

Three-dimensional bonding scheme and associated systems and methods

Semiconductor devices and associated systems and methods are disclosed herein. In some embodiments, the semiconductor device is an assembly that includes a package substrate having a front side and a backside opposite the front side. A controller die with a first longitudinal footprint can be attached to the front side of the package substrate. A passive electrical component is also attached to the front side of the package substrate. A stack of semiconductor dies can be attached to the controller die and the passive electrical component. The stack of semiconductor dies has a second longitudinal footprint greater than the first longitudinal footprint in at least one dimension. The controller die and the passive electrical component are positioned at least partially within the second longitudinal footprint, thereby at least partially supporting the stack of semiconductor dies.

Systems and methods for reducing the size of a semiconductor assembly

An apparatus includes a substrate for mounting an integrated circuit. The substrate includes a primary layer including a first surface that is a first external surface of the substrate. The substrate includes an inner layer that is located below the primary layer and including a second surface. A portion of the second surface of the inner layer is exposed via an open area associated with the primary layer. The inner layer includes a first multiple of wire bond pads that are exposed via the open area associated with the primary layer.

Growing community of inventors

Singapore, Singapore

Seng Kim Ye