Csmc Technologies Fab2 Co., Ltd.

Southeast University

Csmc Technologies Fab1 Co., Ltd.

Other

Apex Brands, Inc.

Nanjing University of Technology

Nanjing University of Chinese Medicine

Sen Zhang

Yan Gu

Shikang Cheng

Nailong He

Guangsheng Zhang

Longxing Shi

Weifeng Sun

Zhili Zhang

Jingchuan Zhao

Bin Wu

Pingkai Ouyang

Wei Su

Jing Zhu

Congming Qi

Jianlin Chu

Xueming Wu

Bingfang He

Lihui Gu

Hao Wang

Guipeng Sun

Shen Xu

Long Zhang

Jie Ma

Jichun Zhou

Shukun Qi

Jinao Duan

Jinyu Xiao

Siyu Zhao

Pei Liu

Sheng Guo

Shaohong Li

Guichuang Zhu

Xuchao Li

Yun Lan

Mingshu Zhang

Jinli Gong

Rui Zhong

Xiaoyu Shi

Hui Yan

Weimeng Feng

Wentong Zhang

Teng Liu

A strain separation method for preventing and controlling early bolting of, and preparation of a microbial agent and use thereof, the strain is obtained by separation, purification and cultivation from rhizosphere soil of, and is identified asspp. by Microbial 16S rDNA sequencing; the strain was deposited at China Center for Type Culture Collection on Jun. 24, 2021 under CCTCC NO: M 2021767; tTheXG3 strain provided by the present invention can promote the seed germination ofand delay the flowering offor about 2 days; according to field test verification, the microbial agent can increase the root weight, root diameter and rootlet number of, can effectively prevent and control early bolting of

strain for preventing and controlling early bolting of, microbial agent and use thereof

A laterally diffused metal-oxide-semiconductor (LDMOS) device and a method for fabricating the LDMOS device are disclosed. The device includes: a substrate () having a second conductivity type; a drift region () that has a first conductivity type and is disposed on the substrate (), wherein the first conductivity type is opposite to the second conductivity type; a plurality of layers of doped structures disposed in the drift region (), each layer of the doped structure comprising at least one doped bar () extending in a lengthwise direction of a conductive channel; and a plurality of doped polysilicon pillars () disposed in the drift region () so as to extend downward through the doped bar () of at least one of the layer of doped structures, wherein ions doped in the doped polysilicon pillars () and ions doped in the doped bar have opposite conductivity types.

Lateral diffusion metal oxide semiconductor device and manufacturing method therefor

The semiconductor device comprises a high-voltage device region, a low-voltage device region, and an isolation region. It further comprises a drift region, a second conductivity type well region, an isolation well region, an isolation structure, a power device source region, and a power device drain region. The drift region is disposed in the high-voltage device region. The second conductivity type well region is disposed in the isolation region and extends to the low-voltage device region. The isolation well region is disposed in the drift region and separates the drift region into a high-voltage drift region and a power device drift region. The isolation structure is disposed in the isolation well region. The power device source region is disposed in the isolation region and located in the second conductivity type well region, and the power device drain region is disposed in the power device drift region.

Semiconductor device and manufacturing method thereof

Disclosed are a laterally diffused metal oxide semiconductor device and a method for preparing the same. The device includes a substrate () of a first conductivity type, a drift region () of a second conductivity type, a longitudinal floating field plate array and a plurality of implantation regions () of the first conductivity type. The drift region is located in the substrate of the first conductivity type. The longitudinal floating field plate array includes a plurality of longitudinal floating field plate structures () arranged at intervals in rows and columns. Each longitudinal floating field plate structures includes a dielectric layer () disposed on an inner surface of a trench and a conductive layer () filling the trench. The plurality of implantation regions are located in the drift region of, each implantation region is located between two adjacent longitudinal floating field plate structures in each row.

Laterally diffused metal oxide semiconductor device and method for preparing the same

A laterally diffused metal-oxide-semiconductor (LDMOS) device and a method of manufacturing the LDMOS device are disclosed. The method includes: obtaining a substrate with a drift region formed thereon, the drift region having a first conductivity type and disposed on the substrate of a second conductivity type; etching the drift region to form therein a sinking structure, the sinking structure includes at least one of an implanting groove and an implanting hole; implanting ions of the second conductivity type at the bottom of the sinking structure; forming a buried layer of the second conductivity type by causing diffusion of the ions of the second conductivity type using a thermal treatment; and filling an electrical property modification material into the sinking structure, the electrical property modification material differs from the material of the drift region.

Laterally diffused metal oxide semiconductor device and manufacturing method therefor

A semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a semiconductor substrate. A first drift region is formed in the semiconductor substrate. A gate structure is formed on the semiconductor substrate A part of the gate structure covers a part of the first drift region. A first trench is formed in the first drift region, and a drain region is formed in the semiconductor substrate at the bottom of the first trench.

Semiconductor device and manufacturing method therefor

An insulated gate bipolar transistor, comprising an anode second conductivity-type region and an anode first conductivity-type region provided on a drift region; the anode first conductivity-type region comprises a first region and a second region, and the anode second conductivity-type region comprises a third region and a fourth region, the dopant concentration of the first region being less than that of the second region, the dopant concentration of the third region being less than that of the fourth region, the third region being provided between the fourth region and a body region, the first region being provided below the fourth region, and the second region being provided below the third region and located between the first region and the body region.

Insulated gate bipolar transistor

A transient voltage suppression device includes: a substrate; a first conductive type well region including a first well and a second well; a second conductive type well region including a third well and a fourth well, the third well being disposed between the first well and the second well so as to isolate the first well and the second well, and the second well being disposed between the third well and the fourth well; a zener diode active region; a first doped region, provided in the first well; a second doped region, provided in the first well; a third doped region, provided in the second well; a fourth doped region, provided in the second well; a fifth doped region, provided in the zener diode active region; and a sixth doped region, provided in the zener diode active region.

Transient voltage suppression device and manufacturing method therefor

A synchronous rectification control system and method for a quasi-resonant flyback converter are provided. The control system includes a switching transistor voltage sampling circuit configured to sample an output terminal voltage of the switching transistor to obtain a sampled voltage of the switching transistor; a sampling calculation module configured to obtain a dead-time based on the sampled voltage of the switching transistor and a preset relationship, the preset relationship being a correspondence between the duration of the sampled voltage of the switching transistor being below a first preset value and the dead-time during an on-time of a switching cycle of the switching transistor, the dead-time being a time from when the switching transistor is turned off to when the synchronous rectification transistor is turned on; and a control module configured to receive the dead-time and control switching of the synchronous rectification transistor based on the dead-time.

Synchronous rectification control system and method for quasi-resonant flyback converter

A transient voltage suppression device and a manufacturing method therefor, the transient voltage suppression device including: a substrate, a first conductivity type well region and a second conductivity type well region disposed in the substrate. The first conductivity type well region includes a first well, a second well, and a third well. The second conductivity type well region includes a fourth well that isolates the first well from the second well, and a fifth well that isolates the second well from the third well. The device further includes a Zener diode well region provided in the first well, a first doped region provided in the Zener diode well region, a second doped region provided in the Zener diode well region, a third doped region provided in the second well, a fourth doped region provided in the third well, and a fifth doped region provided in the third well.

A laterally double-diffused metal oxide semiconductor device is provided, including: a drift region () having a first conductivity type; a first body region () disposed on the drift region () and having a second conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types; a first conductivity type region () disposed in the first body region (); a second body region () disposed in the first conductivity type region () and having the second conductivity type; a source region () disposed in the second body region () and having the first conductivity type; and a contact region () disposed in the first body region () and having the second conductivity type.

Laterally double-diffused metal oxide semiconductor device

A TVS device and a manufacturing method therefor. The TVS device comprises: a first doping type semiconductor substrate (); a second doping type deep well I (), a second doping type deep well II (), and a first doping type deep well () provided on the semiconductor substrate; a second doping type heavily doped region I () provided in the second doping type deep well I (); a first doping type well region () and a first doping type heavily doped region I () provided in the second doping type deep well II (); a first doping type heavily doped region II () and a second doping type heavily doped region II () provided in the first doping type deep well (); a second doping type heavily doped region III () located in the first doping type well region () and the second doping type deep well II (); and a first doping type doped region () provided in the first doping type well region ().

TVS device and manufacturing method therefor

A trench gate depletion-type VDMOS device and a method for manufacturing the same are disclosed. The device comprises a drain region; a trench gate including a gate insulating layer on an inner wall of a trench and a gate electrode filled in the trench and surrounded by the gate insulating layer; a channel region located around the gate insulating layer; a well region located on both sides of the trench gate; a source regions located within the well region; a drift region located between the well region and the drain region; a second conductive-type doped region located between the channel region and the drain region; and a first conductive-type doped region located on both sides of the second conductive-type doped region and located between the drift region and the drain region.

Trench gate depletion mode VDMOS device and method for manufacturing the same

A method and an apparatus for reducing noise of a switched reluctance motor, includes: supplying a PWM signal as a driving signal to a driving circuit of a switched reluctance motor; and varying a carrier frequency of the PWM signal as an operation period of the switched reluctance motor varies; if the switched reluctance motor changes phase, determining that the operation period of the switched reluctance motor varies.

Method for reducing noise of a switched reluctance motor based on adjusting a PWM carrier frequency

A manufacturing method of an LDMOS device comprises: obtaining a wafer formed with a doped region having a first conductivity type, wherein a top buried layer is formed inside the doped region having the first conductivity type, and a field oxide insulation layer structure is formed on the top buried layer; disposing a trench on the doped region having the first conductivity type, wherein the trench extends to the top buried layer and the field oxide insulation layer structure such that a portion of the top buried layer is removed; injecting an ion of a second conductivity type to form a well region below the trench; and forming a doped source region in the well region. The first conductivity type and the second conductivity type are opposite conductivity types.

Method of manufacturing an LDMOS device having a well region below a groove

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Wuxi New District, China

Sen Zhang