Integrated Device Technology, Inc.

Cypress Semiconductor Corporation

Synaptics Corporation

Sen-Jung Wei

Kuang-Yu Chen

Jonathan Ku

Shao-Jen Lim

An output clock recovery circuit () for recovering an output clock () from a source clock () and time stamp information (A,B) includes a time stamp translator () and a phase-locked loop circuit () including a fraction processor (). The time stamp translator () receives the time stamp information (A,B) and uses an algorithm that translates the time stamp information (A,B) into a time stamp decimal component () and a time stamp integer component (). The time stamp decimal component () is less than one and is processed by the fraction processor (). The time stamp integer component () is maintained within a predetermined range of integers that are greater than zero. The output of the fraction processor () and the time stamp integer component () can be input into a feedback divider () of a feedback loop of the phase-locked loop circuit () to recover the output clock (). The fraction processor () can include a fraction accumulator or a delta-sigma type of fractional-N phase-locked loop circuit.

Circuit for recovering an output clock from a source clock

A phase-locked loop includes a sample selector configured to select a set of samples from an oversampled portion of a data signal, a dynamic phase decision control circuit configured to indicate whether a predetermined number of edges is present in the set of samples, and a phase detector configured to determine a skew condition and a direction of the skew condition of the set of samples based on the indication of the dynamic phase decision control circuit. The phase detector is configured to produce a set of skew detection signals based on at least one skew condition determination. The phase-locked loop further includes a loop filter configured to filter the set of skew detection signals. The loop filter is also configured to produce a set of phase adjustment signals based on the set of skew detection signals. The sample selector is configured to select a set of samples from the oversampled portion of the data signal, based on the set of phase adjustment signals. In one embodiment, the dynamic phase decision control circuit is also configured to detect an absence of edges in the set of samples, and a state change of the loop filter is inhibited according to the indication of the absence of edges.

Dynamic phase tracking using edge detection that employs an edge counter

A phase-locked loop includes a sample selector configured to select a set of samples from an oversampled portion of a data signal, a dynamic phase decision control configured to indicate whether a predetermined number of edges is present in the set of samples, and a phase detector configured to determine a skew condition and a direction of the skew condition of the set of samples based on the indication of the dynamic phase decision control. The phase detector is configured to determine a skew condition based on a relation between a threshold and a number of skew errors detected in the set of samples. A value of the threshold is selected according to the indication of the dynamic phase decision control. A lower value of the threshold is selected according to an indication of the dynamic phase decision control that only one edge is present in the set of samples. Furthermore, the dynamic phase decision control includes an edge detector configured to detect edges in the set of samples, and an edge counter configured to indicate the detection of the predetermined number of edges in the set of samples. Methods of determining a skew condition and a direction of the skew condition, and methods of determining whether a predetermined number of edges is present in the set of samples, are implemented using these elements.

Dynamic phase tracking using edge detection

The application discloses driver circuits including a current source, a current sink, and a current steering circuit configured to provide current to a load. The current sink is configured to be controlled according to a regulated voltage. Signal generator circuits are also disclosed.

Differential signaling transmission circuit

A circuit and/or method comprising an oscillator circuit, a pulse detection circuit and a control circuit. The oscillator circuit may be configured to generate an output signal having a frequency in response to (i) a first control signal and (ii) a second control signal. The pulse detection circuit may be configured to generate a detect signal in response to the output signal. The control circuit may be configured to generate the second control signal in response to said detect signal.

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San Jose, CA, United States of America

Sen-Jung Wei