Ovonyx Inc.

Intel Corporation

Stmicroelectronics S.r.l.

Ovonyx Memory Technology, LLC

Carlow Innovations LLC

Semyon D Savransky

Ilya V Karpov

Tyler A Lowrey

James Reed

Sergey A Kostylev

Gianpaolo Spadini

George A Gordon

Ward D Parkinson

Ward M Parkinson

Stanford R Ovshinsky

David L Kencke

Jason S Reid

Kuo-Wei Chang

Disturb from the reset to the set state may be reduced by creating an amorphous phase that is substantially free of crystal nuclei when programming the reset state in a phase change memory. In some embodiments, this can be achieved by using a current or a voltage to program that exceeds the threshold voltage of the phase change memory element, but does not exceed a safe current voltage which would cause a disturb.

Immunity of phase change material to disturb in the amorphous phase

A seasoned phase change memory has been subjected to a longer pulse to adjust resistance levels prior to use of the phase change memory.

Seasoning phase change memories

A phase change memory in the reset state may be heated to reduce or eliminate electrical drift.

Reducing temporal changes in phase change memories

A method for manufacturing a phase change memory includes forming a phase change memory cell by forming a phase change layer between two switching layers. The phase change layer is separated from thermal heat sinks, such as the bitline or wordline, by the switching layers.

Self-heating phase change memory cell architecture

Chalcogenide materials conventionally used in chalcogenide memory devices and ovonic threshold switches may exhibit a tendency called drift, wherein threshold voltage or resistance changes with time. By providing a compensating material which exhibits an opposing tendency, the drift may be compensated. The compensating material may be mixed into a chalcogenide, may be layered with chalcogenide, may be provided with a heater, or may be provided as part of an electrode in some embodiments. Both chalcogenide and non-chalcogenide compensating materials may be used.

Reducing drift in chalcogenide devices

A chalcogenide alloy that optimizes operating parameters of an ovonic threshold switch includes an atomic percentage of arsenic in the range of 9 to 39, an atomic percentage of germanium in the range of 10 and 40, an atomic percentage of silicon in the range of 5 and 18, an atomic percentage of nitrogen in the range of 0 and 10, and an alloy of sulfur, selenium, and tellurium. A ratio of sulfur to selenium in the range of 0.25 and 4, and a ration of sulfur to tellurium in the alloy of sulfur, selenium, and tellurium is in the range of 0.11 and 1.

Ovonic threshold switch film composition for TSLAGS material

A phase change memory may be formed with an insulator made up of two different layers having significantly different thermal conductivities. Pores may be formed within the stack of insulating layers and the pores may be filled with heaters, chalcogenide layers, and electrodes in some embodiments. The use of the two different insulator layers enables embodiments where thermal losses may be reduced and an amorphous region may be maintained along the entire length of the phase change material layer.

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Newark, CA, United States of America

Semyon D Savransky