Alliedsignal Inc.

Other

Washington University

Allied Corporation

The Bendix Corporation

Semyon Berkovich

Chris J Walter

Colleen R Wilson

Henry C Yee

Efraim Berkovich

Richard A Burne

Murray H Loew

In a multi-processor computing system, a multi-layer architecture is described in which each layer has a plurality of dual ported microprocessors, one port of which receives data for processing and the other port of which is utilized for unloading or passing data to a subsequent layer. If the processing cannot be completed prior to the time allotted for the next load cycle for a particular processor, the processing is interrupted, the state of the processor currently engaged in the processing is stored in the data and the state of the processor is transferred to a processor of a subsequent layer where processing resumes as if no interruption had occurred.

Multi-layer multi-processor information conveyor with periodic

A computing system having a plurality of processing elements for concurrent execution of a serial program is able to run applications developed for single processors without change to source code or object code by allocating instructions to various processors depending upon the addresses contained within their operand(s). The memory space of the system is partitioned into individual memory blocks which are controlled by dedicated memory coordination units and plural memory coordination units are associated with each processor in a combinatorial connection arrangement. This allows instructions to execute on processors which inherently have all the information needed in their registers at the time of execution thus enhancing performance. The plurality of memory coordination units connected to a processing element are associated with FIFO queues which are utilized to ensure sequential consistency including the cases of indirect addressing and conditional jumps.

Methods and apparatus for concurrent execution of serial computing

An information processing unit having a memory (16) storing a set of data elements in a data lattice structure. The memory is content-addressably searched by a pair of processors (12) and (14) controlling confronting traversals of the data lattice structure. A traversal controller (24) generates a search routine for the two processors (12) and (14) resulting in a natural two-way concurrency in their operation. A second memory (22) stores processing instructions and pointers used by the traversal controller (24) to generate the search routine. The processing instructions and pointers are extracted from the second memory under the control of processors (18) and (20). An interface processor (26) is connected to a communication link (28) connecting the information processing unit to utilization devices.

Retrieval of information from lattice-structured content-addressable

A communication method and apparatus incorporating fault-tolerance and increased transmission reliability in a content-induced transaction overlap (CITO) system is disclosed. The system is driven by an error-detecting and correcting CITO-based protocol whereby transient failures are transparent to the user. A parity check is built into the protocol for detecting failures due to hard faults. A redundancy configuration is also disclosed which permits circumvention of fabrication defects, thereby allowing an increased manufacturing yield.

Fault-tolerant CITO communication system

A computer communication bus system having a communication bus (10) having a plurality of data transmission lines (26, 28, 30) and a plurality of transmission nodes (12, 14, 16, 18) connected to the communication bus (10). Each transmission node (12, 14, 16, 18) has a data source providing multi-bit data to be transmitted on the communication bus (10), a plurality of data transformers (42, 44, 46) for encoding or transforming the multi-bit data into different multi-bit encoded data formats, and a plurality of CITO transmitters for transmitting the transformed data on different data transmission lines (26, 28, 30) using a content induced transaction overlap (CITO) protocol. Using the CITO protocol, the CITO transmitters (20, 22, 24) transmit the same data on each of the transmission lines (26, 28, 30) in a different order.

Computer communication bus system using multiple content induced

A processing system using a number of distributed memory modules each connected through a sending device to a common serial communication bus. The memory modules each include conventional random access memories (RAMs) and custom designed controllers capable of unloading data encoded in a content induced transaction overlap (CITO) format from the RAM to a the sending device for serial transmission according to a CITO protocol.

Computer system with distributed RAM memory modules designed for CITO

A processing system using a number of distributed associative (content addressable) memory modules each connected through a sending device to a common serial communication bus. The memory modules are custom designed to unload stored data to a central receiver using a content induced transaction overlap (CITO) transmission.

Computer system with distributed content-addressable memory modules

A processing system using a number of distributed associative (content addressable) memory modules each connected through a sending device to a common serial communication bus. The memory modules are concurrently accessible by a central receiver. Data accessed from each memory module is compressed according to content induced transaction overlap (CITO) format, and the compressed data is serially communicated to the receiver according to a CITO protocol.

Computer system with distributed content-addressable memory

A simple mechanism for a CITO communication channel with a possibility to use variable length messages which combines different control functions; bootstrapping, synchronization, and interrupts is disclosed. The mechanism introduces and maintains synchronization of the CITO communication channel by actively interrupting and restarting the transmission process.

Technique for active synchronization of the content induced transaction

A method and apparatus is described for distributing data in a hierarchically connected system (10) comprising a plurality of nodes (12-25) at each of a plurality of hierarchical levels, one or more bidirectional buses (29-30, 31,32) interconnecting mutually exclusive nodes at each hierarchical level, and a sender (49) for receiving and transmitting data located at each node (12-25) for transmitting and receiving data under the Content Induced Transaction Overlap (CITO) protocol and for transmitting and receiving data without regard to the CITO protocol. Each bidirectional bus (27-32) is interconnected through a node to a node on a bidirectional bus at a higher hierarchical level. Several virtual buses may be formed for distribution of the messages over one or more bidirectional buses (27-33) by controlling the senders (90,92,94,96) at each node by a slot controller (88) which activates the senders (90,92,94,96) as a function of time slot. The invention overcomes the problem of distributing data to all nodes (12-25) in a hierarchically connected system as well as to nodes (14-17 ) at a selected hierarchical level or to nodes (18-19) hierarchically connected subordinate to a node (14).

Multilevel concurrent communications architecture for multiprocessor

A content induced transaction overlap communication (CITO) system for transmitting data over a single communication channel permits priority queuing for Senders having critical values. In one configuration, those Senders sensing the critical values transmit a word indicating the critical condition, and polling is limited to a group of sensors which include the sensor subject to the critical value.

Priority queuing technique for content induced transaction overlap

An on-the-fly data compression system for compressing the data transmitted between a data source and an ultimate utilization device. The system normally has two data compression modules implementing a conventional multi-buffering scheme and a decoder for reconstructing the compressed data to its original format. The data compression modules compresses the data using a word representation by associative processing buffer and a content induced transaction overlap transmission protocol which results in an interleaved transmission of data bits and bit position bits, the latter being indicative of the number of data bits that will be transmitted during the subsequent data transmission. The decoder reconstructs the compressed data to its original format in response to the transmitted data and bit position bits and stores them in a pair of buffers in the sequential order in which they were generated.

On-the-fly data compression system

A content induced transaction overlap communication system for transmitting data over a single communication channel between a plurality of senders and at least one receiver. The senders simultaneously transmit the highest order bits of their data word, one bit at a time in serial fashion and monitor the state of the communication channel. Transmission of data bits is terminated by all senders which detect a difference between the state of their transmitted data bit and the state of the communication channel. Bit competition performed at the end of each transmitted data word determines among those senders still having data bits remaining to be transmitted which sender has lexicographically the next smallest word and activates that sender to transmit its remaining data bits. This procedure continues until all of the senders have completed the sending of their data word.

Growing community of inventors

Rockville, MD, United States of America

Semyon Berkovich