Guzik Technical Enterprises

Semen P Volfbeyn

Anatoli B Stein

Alexander M Taratorin

Valeriy Serebryanskiy

Nahum E Guzik

Igor Tarnikov

Vladislav Anatolievich Klimov

Sergey Konshin

A digital equalizer with reduced number of multipliers for correction of the frequency responses of an interleaved analog-to-digital-converter (ADC) is disclosed. An exemplary interleaved analog to digital converter with digital equalization includes at least one composite ADC including M time-interleaved sub-ADCs, and an equalization configuration deploying a Pre-FIR transformers unit, a FIRs assembly unit, and a Post-FIR transformers unit. The FIRs assembly unit includes a finite impulse response (FIR) filter network which is operative pursuant to a Fast Filtering Algorithm as an alternative to a conventional finite impulse response network, enabling a reduction of the number of multipliers compared to conventional FIR filter-based equalization networks for ADCs.

Time interleaved analog to digital converter with digital equalization and a reduced number of multipliers

A method and system for calibrating a time-interleaved digital to analog converter (DAC) provides equalization of frequency response misalignments in sub-DACs forming the DAC. In a calibration mode, test signals are applied to an DAC and output amplitudes and phases of are measured. From the measured values, complex values of the gains of the respective sub-DACs. h(F) are determined and a specified target frequency response T(F) for a tandem connection equalizer-DAC is determined. For each of a plurality of test frequencies, complex values of equalizer gains Eqare determined from Eq(F)=T(F)/h(F), to form equalizing frequency responses. Sets of equalizing coefficients C(p) pursuant to discrete Fourier transforms on Eq(F). In an operation mode, a digital input signal is transformed input into an equalized digital signal E(n) through use of the sets of equalizing coefficients C(p).

Equalization of sub-DAC frequency response misalignments in time-interleaved high-speed digital to analog converters

A digital down-converter with baseband equalization comprises a composite analog-to-digital converter (ADC) adapted to convert an applied RF analog signal to be processed to a digital signal, and then down-convert the digital signal to a baseband frequency region, and then perform equalization on the down-converted digital signal, thereby reducing distortions caused by introduction of spurious signals by the ADC.

Digital down converter with baseband equalization

Measurement of group delay for a device under test (DUT). A test signal includes (i) a low frequency sine wave f, (ii) sine wave harmonics at a high frequency f, (iii) L pairs of sideband components at frequencies k&#xb7;f&#xb1;2&#xb7;f, where k odd, and M pairs of sideband components at frequencies k&#xb7;f&#xb1;f, where k is even. At DUT output, (i) phase &#x3d5;at frequency fis measured, (ii) both sideband phase &#x3d5;(k) at frequencies k&#xb7;f+2&#xb7;fand phase &#x3d5;(k) at frequencies k&#xb7;f&#x2212;2&#xb7;ffor odd k, are measured, and (iii) both sideband phases &#x3d5;(k) at frequencies k&#xb7;f+fand &#x3d5;(k) at frequencies k&#xb7;f&#x2212;ffor even k, are measured. Group delay &#x3c4;at frequencies k&#xb7;F, are determined from: &#x3c4;=(&#x3d5;(k)&#x2212;&#x3d5;(k)&#x2212;4&#xb7;&#x3d5;)/(4&#xb7;f) for k odd, and &#x3c4;=(&#x3d5;(k)&#x2212;&#x3d5;(k)&#x2212;2&#xb7;&#x3d5;)/(2&#xb7;f) for k even.

Group delay measurement apparatus and method

A digital down converter with an equalizer translates an ADC output signal to a low frequency spectral region, followed by decimation. All operations of correction of the processed signal are carried out with a reduced sampling rate compared with sampling rates of the prior art. Equalization is performed only in a frequency pass band of the down converter. The achieved reduction of the required computation resources is sufficient to enable the down converter with equalization to operate in a real time mode.

Digital down converter with equalization

A digital down converter with equalization includes a composite ADC that performs demodulation of a received analog signal, converting the signal into in phase baseband signal and quadrature baseband signal. Equalization is performed to correct for misalignment of the frequency responses of the sub-ADCs in the composite ADC. In a form, ADC output signals are applied to a mixer array to frequency down-shift the digital form of the input signal, followed by digital filtering to effect convolutions of portions of the digital form of the input signal with a set of convolution coefficients determined so that the net processing is mathematically equivalent to down conversion with equalization. In another form, the ADC output signals are directly applied to a digital filter to effect both frequency down-shifting and convolutions, with filter coefficients determined so that the net processing is mathematically equivalent to down conversion with equalization.

An acquisition device includes an analog to digital converter (ADC) composed of multiple interleaved ADCs (sub-ADCs), which receives an analog signal which is converted to digital form. The digitized signal is processed seriatim by a pre-(or trigger-) equalizer, an acquisition memory and a post-(or memory) equalizer. In a calibration mode, frequency responses of the respective sub-ADCs are determined and trigger coefficients are determined for application to the trigger equalizer to effect a preliminary equalization of the digitized signal sufficient to permit operation of the trigger processor in an acquisition mode. Memory coefficients are determined based on residual frequency responses of the sub-ADCs, for application to the memory equalizer. A trigger processor is responsive to the trigger equalizer to select a subset of samples of the digitized signal for loading to the acquisition memory. The trigger equalizer and a memory equalizer are configured for consecutive operation so that, in an acquisition mode, the memory equalizer receives as its input, a digitized signal from the ADC that has been pre-processed in the trigger equalizer, and the memory equalizer corrects only the residue of misalignments and frequency distortions that remain after the trigger equalizer operation.

Acquisition device with multistage digital equalization

An analog to digital conversion device with DC offset mismatch compensation comprises a composite analog to digital converter (ADC) consisting of N interleaved sub-ADCs, a DC offset accumulator, an averaging unit, a subtraction unit, and a compensation unit. The ADC generates a stream of digital samples corresponding to signal values at an analog input to the ADC. The digital stream is a combination of N partial signals produced by the respective sub-ADCs. The DC offset accumulator measures and stores DC offsets of the respective partial signals. The averaging unit calculates an average value of DC offsets of the respective N partial signals. The subtraction unit is responsive to the DC offsets of the respective partial signals and the average value of the DC offsets, to produce a signal representative of the differences between the values arriving at a DC offset input and the value arriving at an average value input. The subtraction unit is responsive to the DC offsets of the respective partial signals and the average value of the DC offsets, to produce a signal representative of the differences between the values arriving at the DC offset input and the value arriving at the average value input. The compensation unit corrects the digital stream from the ADC by subtracting the differences from the stream from the ADC.

High speed interleaved ADC with compensation for DC offset mismatch

A digital down converter with equalization includes an analog to digital converter (ADC), a frequency divider, an FIR-decimator-I, an FIR-decimator-Q and a frequency corrector. In operation, after some preprocessing, the FIR-decimator-I performs signal transformation equivalent to a sequence of equalization, multiplication of the processed signal by a sine wave of a conversion frequency and low pass filtering, and the FIR-decimator-Q performs signal transformation equivalent to a sequence of equalization, multiplication of the processed signal by a sine wave of conversion frequency with a phase shift of 90&#xb0; and low pas filtering. The transformed signals are applied to the frequency corrector, which provides a frequency shift of predetermined value with respect to a nominal carrier frequency of the applied analog input signal and generates an In-Phase output and a Quadrature output.

A synchronization system for initial setup of phases of local oscillators in a wireless receiver of a communication system characterized by transmission of data packets having a predetermined preamble consisting of M identical sections of L symbols followed by a single section of the same kind, multiplied by &#x2212;1, and wherein the wireless receiver is operative to perform decimation in an RF demodulator. The synchronization system includes a twofold correlator, an accumulator, a multipler, a threshold comparator, a carrier phase former and a clock phase former, and operates at a decimated symbols frequency, and performs not only preamble detection, but also symbols clock phase detection together with carrier phase detection, while enabling the theoretically possible noise immunity.

Synchronization system for a wireless receiver

A digital equalizer with a reduced number of multipliers for correction of the frequency responses of an interleaved ADC is disclosed. An exemplary interleaved analog to digital converter with digital equalization includes a composite ADC including M time interleaved sub-ADC, a demultiplexer, samples repositioning unit, a first PreFIRs transformer, a second PreFIRs transformer, K double buffer FIR filters, a PostFIRs transformer, a samples sequence restoration unit, and a multiplexer, coupled in series and providing an equalized, frequency response-corrected output.

Interleaved analog to digital converter with reduced number of multipliers for digital equalization

An interleaved analog to digital converter with digital equalization includes a conversion-measurement-equalization unit and residual distortions reduction unit, and is operative in a calibration mode and converter mode. The conversion-measurement-equalization unit includes a composite ADC containing N sub-ADCs, equalizer, responses measurement unit and a coefficients calculator. The residual distortions reduction unit uses received measured frequency responses and equalizer coefficients, both from the conversion-measurement-equalization unit, as a base to calculate corrected frequency responses that are applied to the coefficients calculator for generation of equalizer coefficients for application to the equalizer. A residual distortions calculator of the residual distortions reduction unit, is responsive to measured frequency responses from the composite ADC and a current set of equalizer coefficients applied to the equalizer, to calculate residual frequency distortions that should have been expected to appear in the output signal of the ADC system if the current equalizer coefficients remain applied to the equalizer.

Interleaved analog to digital converter with digital equalization

A write clock generator for use in writing data to a rotating patterned magnetic media disk is disclosed. The generator includes a magnetic read head for generating a succession of servo signals representative of succession of servo magnetization patterns detected from a corresponding succession of arcuate sectors along a circular data track on the disk. A preamble processor generates a corresponding succession of sector pair signals representative of the lengths of adjacent sectors along the data track on a rolling pair-wise basis. A next sector length predictor processor determines for a succession of pairs of sectors, a length ratio of the lengths of the sectors in the respective pairs of sectors. A clock generator generates a periodic clock for each sector of the succession of sectors, wherein the clock rate associated with a current sector has an associated phase deviation relative to a clock rate associated with a previous sector, which is proportional to the length ratio for the current sector and the previous sector.

Write clock synchronization appartus for magnetic recording disk drives with patterned media

A vector signal generator with direct RF signal synthesis is disclosed. The vector signal generator comprises an RF signal synthesizer, a switch, and a memory. The RF signal synthesizer is configured for converting baseband IQ signals into a modulated digital RF signal. The RF signal synthesizer is connected to an I input, a Q input, a clock input, a control input, and an output, where the clock input is a clock input of the vector signal generator, the control input is a control input of the vector signal generator, and the output is an RF signal output of the vector signal generator. The switch is configured for selecting a source of IQ signals and is connected to an external I input, an external Q input, a stored signal I input, a stored signal Q input, the control input, an I output, and a Q output. The external I input and external Q input are external IQ inputs to the vector signal generator and the I output and the Q output are connected to the I input and the Q input of the RF signal synthesizer. The memory is configured for storing IQ signals samples, said memory being connected to the control input and having a stored I output, connected to the stored signal I input, and a stored Q output connected to the stored signal Q input.

Method and system of vector signal generator with direct RF signal synthesis and parallel signal processing

Disclosed is a method of equalization of a vector/signal analyzer including: providing a structured test signal within a selected frequency range. The structured test signal includes a plurality of frequency components each having a respective amplitude and phase. The method includes inputting the test signal to the analyzer; the analyzer operating to condition the test signal; determining information representative of frequency distortion of the conditioned test signal introduced by the analyzer; generating a set of equalization coefficients based on the information representative of the frequency distortion, the set of coefficients corresponding to the selected frequency range; and storing the set of equalization coefficients and the correspondence of the set of coefficients to the selected frequency range.

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Palo Alto, CA, United States of America

Semen P Volfbeyn