Intel Corporation

Selvakumar Panneer

Carl S Marshall

Glen J Anderson

Reshma Lal

Pradeep M Pappachan

Varghese George

Sujoy Sen

Luis S Kida

Robert O Sharp

Soham Jayesh Desai

Prasoonkumar Surti

Giuseppe Beppe Raffa

Scott R Janus

Ravishankar Iyer

Saurabh Tangri

Jill MacDonald Boyce

Adam T Lake

Deepak Shashidhar Vembar

Karthik Veeramani

Mike MacPherson

Meng Shi

Nilesh K Jain

Abhishek R Appu

Joydeep Ray

Altug Koker

Elmoustapha Ould-Ahmed-Vall

Ben J Ashbaugh

Vallabhajosyula S Somayazulu

Hugues Labbe

Sameer Kp

Sangita R Sharma

Srenivas Varadarajan

Zhijun Lei

Sherine Abdelhak

Susanta Bhattacharjee

Zhengmin Li

Darrel K Palke

Mrinalini Attaluri

Vasanth Ranganathan

John H Feit

Aravindh V Anantaraman

Daniel Pohl

Lakshminarayanan Striramassarma

Venkat R Gokulrangan

Ankur Agrawal

Soethiha Soe

Jeffrey R Jackson

Zack Waters

Andrea E Johnson

Mrutunjayya Mrutunjayya

Subramaniam M Maiyuran

Ravi L Sahita

Rajesh Poornachandran

Travis T Schluessler

Kamal Sinha

Ankur N Shah

Eric C Samson

Nicolas C Galoppo Von Borries

Yong Jiang

Omesh Tickoo

Abhishek Venkatesh

Pattabhiraman K

Josh B Mastronarde

Niranjan L Cooray

Valentin Andrei

Brent E Insko

Rajeev K Nalawadi

Lama Nachman

Lenitra M Durham

Rameshkumar G Illikkal

Arthur Hunter, Jr

Toby Opferman

Roksana Golizadeh Mojarad

Salmin Sultana

Rahuldeva Ghosh

John W Sherry

Yuanyuan Li

Abhay A Dharmadhikari

Vijay Bahirji

Jayakrishna P S

Fan Chen

Adam Z Leibel

Nilay Mistry

Rajabali Koduri

Satyam Srivastava

Danyu Bi

Brandon Gavino

Amin Heydarpour

Vinay Nooji

Makarand Dharmapurikar

Pramod Pesara

Tion A Thomas

Alexandra Warlen

Honnesh Rohmetra

Shi Meng

Scott G Christian

Rajeev Penmatsa

A method includes receiving a request for a transfer of data on a bus of a computing device; determining a direction for the transfer, at least in part based on the request; determining a quantity of data for the transfer, at least in part based on the request; determining a power state for a lane of the bus, at least in part based on the direction and the quantity of data for the transfer; and setting the power state for the lane of the bus.

Per-lane power management of bus interconnects

An apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. The apparatus includes one or more processors to: provide a remote GPU middleware layer to act as a proxy for an application stack on a client platform that is separate from the remote server platform, wherein the remote GPU middleware layer comprises is to expose an abstraction of the remote GPU to userspace components of a remote GPU stack, the userspace components running on the client machine; communicate with a kernel mode driver of the one or more processors to cause the host memory to be allocated for data structures used to communicate commands between the client and the remote GPU; and invoke the kernel mode driver to submit a workload generated by the application stack, the workload submitted for processing by the remote GPU using the data structures allocated in the host memory.

Disaggregated computing for distributed confidential computing environment

A computing platform is disclosed. The computing platform includes a first computer system comprising a first graphics processing unit (GPU), a network coupled to the first computer system and a second computer system, coupled to the first computer system via the network, comprising a second GPU, wherein the first and second computer system are configured to perform distributed processing of graphics workloads between the first GPU and the second GPU.

Dynamic resource management mechanism

An apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. The apparatus includes a graphics processing unit (GPU) to: provide a virtual GPU monitor (VGM) to interface over a network with a middleware layer of a client platform, the VGM to interface with the middleware layer using a message passing interface; configure and expose, by the VGM, virtual functions (VFs) of the GPU to the middleware layer of the client platform; intercept, by the VGM, request messages directed to the GPU from the middleware layer, the request messages corresponding to VFs of the GPU to be utilized by the client platform; and generate, by the VGM, a response to the request messages for the middleware client.

An apparatus to facilitate inferred object shading is disclosed. The apparatus comprises one or more processors to receive rasterized pixel data and hierarchical data associated with one or more objects and perform an inferred shading operation on the rasterized pixel data, including using one or more trained neural networks to perform texture and lighting on the rasterized pixel data to generate a pixel output, wherein the one or more trained neural networks uses the hierarchical data to learn a three-dimensional (3D) geometry, latent space and representation of the one or more objects.

Inferred shading mechanism

An apparatus to facilitate video motion smoothing is disclosed. The apparatus comprises one or more processors including a graphics processor, the one or more processors including circuitry configured to receive a video stream, decode the video stream to generate a motion vector map and a plurality of video image frames, analyze the motion vector map to detect a plurality of candidate frames, wherein the plurality of candidate frames comprise a period of discontinuous motion in the plurality of video image frames and the plurality of candidate frames are determined based on a classification generated via a convolutional neural network (CNN), generate, via a generative adversarial network (GAN), one or more synthetic frames based on the plurality of candidate frames, insert the one or more synthetic frames between the plurality of candidate frames to generate up-sampled video frames and transmit the up-sampled video frames for display.

Video smoothing mechanism

An apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. The apparatus includes one or more processors to facilitate receiving a manifest corresponding to graph nodes representing regions of memory of a remote client machine, the graph nodes corresponding to a command buffer and to associated data structures and kernels of the command buffer used to initialize a hardware accelerator and execute the kernels, and the manifest indicating a destination memory location of each of the graph nodes and dependencies of each of the graph nodes; identifying, based on the manifest, the command buffer and the associated data structures to copy to the host memory; identifying, based on the manifest, the kernels to copy to local memory of the hardware accelerator; and patching addresses in the command buffer copied to the host memory with updated addresses of corresponding locations in the host memory.

One embodiment provides a graphics processor comprising a block of execution resources, a cache memory, a cache memory prefetcher, and circuitry including a programmable neural network unit, the programmable neural network unit comprising a network hardware block including circuitry to perform neural network operations and activation operations for a layer of a neural network, the programmable neural network unit addressable by cores within the block of graphics cores and the neural network hardware block configured to perform operations associated with a neural network configured to determine a prefetch pattern for the cache memory prefetcher.

Graphics architecture including a neural network pipeline

One embodiment provides a method comprising, at a runtime library executed by a processor of a data processing system, receiving an input frame having objects to be stylized via a style transfer network associated with the runtime library, wherein the style transfer network is a neural network model trained to apply one or more visual styles to an input frame, performing instance segmentation on the input frame to generate one or more instance masks to identify one or more objects to be stylized, generating one or more stylized frames for each style to transfer to the input frame, and merging, via the one or more instance masks, stylized objects from one or more stylized frames with un-stylized content from the input frame to generate an output frame with per-instance stylization.

Real-time temporally consistent object segmented style transfer in media and gaming

Embodiments described herein include software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to distribute memory output based on memory chip thermals. One embodiment provides techniques to enable thermally aware workload scheduling. One embodiment provides techniques to enable end to end contracts for workload scheduling on multiple GPUs.

Graphics processor operation scheduling for deterministic latency

An apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. The apparatus includes a programmable integrated circuit (IC) comprising secure device manager (SDM) hardware circuitry to: receive a tenant bitstream of a tenant and a tenant use policy for utilization of the programmable IC via the tenant bitstream, wherein the tenant use policy is cryptographically bound to the tenant bitstream by a cloud service provider (CSP) authorizing entity and signed with a signature of the CSP authorizing entity; in response to successfully verifying the signature, extract the tenant use policy to provide to a policy manager of the programmable IC for verification; in response to the policy manager verifying the tenant bitstream based on the tenant use policy, configure a partial reconfiguration (PR) region of the programmable IC using the tenant bitstream; and associate a slot ID of the PR region with the tenant use policy.

Embodiments are generally directed to a multi-tile architecture for graphics operations. An embodiment of an apparatus includes a multi-tile architecture for graphics operations including a multi-tile graphics processor, the multi-tile processor includes one or more dies; multiple processor tiles installed on the one or more dies; and a structure to interconnect the processor tiles on the one or more dies, wherein the structure to enable communications between processor tiles the processor tiles.

Multi-tile architecture for graphics operations

Multi-tile Memory Management for Detecting Cross Tile Access, Providing Multi-Tile Inference Scaling with multicasting of data via copy operation, and Providing Page Migration are disclosed herein. In one embodiment, a graphics processor for a multi-tile architecture includes a first graphics processing unit (GPU) having a memory and a memory controller, a second graphics processing unit (GPU) having a memory and a cross-GPU fabric to communicatively couple the first and second GPUs. The memory controller is configured to determine whether frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU in the multi-GPU configuration and to send a message to initiate a data transfer mechanism when frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU.

Multi-tile memory management for detecting cross tile access providing multi-tile inference scaling and providing page migration

Growing community of inventors

Portland, OR, United States of America

Selvakumar Panneer