Intel Corporation

Selim Bilgin

Robert J Safranek

Shaun M Conrad

Sanjay Dabral

Venkatraman Iyer

Theodore Zale Schoenborn

Jeffrey R Wilcox

Naveen Cherukuri

Robin Tim Frodsham

David Stewart Dunning

Lily Pao Looi

Jeffrey Charles Swanson

Stephan Jourdan

Srikanth T Srinivasan

Amit A Merchant

Aaron T Spink

Anant S Deval

Sin Sim Tan

Brinkley Sprunt

David D Dunning

Robert Safranck

Stephan J Jourdan

Methods and apparatus relating to link power savings with state retention are described. In one embodiment, one or more components of two agents coupled via a serial link are turned off during idle periods while retaining link state in each agent. Other embodiments are also disclosed.

Link power savings with state retention

Techniques to cause a point-to-point link between system components to engage in a negotiation process that may lead to the link transitioning from an active state in which data may be transmitted between system components to a low power state where data may not be transmitted. The negotiation process may occur between each pair of nodes within an electronic system that are interconnected via point-to-point link. The negotiation may ensure that there are no pending transactions or transactions that may occur within an upcoming period of time. Through this negotiation each component acknowledges and agrees to transition the link to the low power state.

Techniques for entering a low-power link state

To address the need for power management, the following facilitates maintaining power states in an efficient manner based at least in part on managing packets at different layers of an input/output interface that supports multiple layers. One specific example prevents a destructive event for link layer control logic because packets and information might have been lost or dropped due to a hang condition and/or a dropped packet. In yet another example of power management, this facilitates a low power platform state by preventing the loss of packets or data upon exiting a platform power state upon initiation of a link reset condition by preventing certain types of packets from reaching link layer controller logic.

Method, apparatus, and system for enabling platform power states

Methods and apparatus for integration of a processor and an input/output hub are described. In one embodiment, a sideband signal may cause change in a power management state of a processor or an integrated I/O logic. A single integrated circuit die may include both the processor and the integrated I/O logic. Other embodiments are also disclosed.

Integration of processor and input/output hub

Techniques for dynamically adjusting point-to-point link width based, at least in part, on link conditions. When operating at full power and at the highest performance level, the full width of a point-to-point link may be utilized to transmit data between the end points. If the link is not fully utilized, a portion (e.g., one half or one quarter) of the link may remain active for communication purposes.

Dynamic link width modulation

Methods and apparatus to manage communication bus power states are described. In one embodiment, an apparatus comprises a bus including a master node and at least a first slave node, logic to transmit a first power state change request from the master node to the first slave node, logic to receive the first power state change request in the first slave node, and logic to designate the first slave node as the master node when the first slave node denies the first power state change request.

Communication bus power state management

A system and method for reduced power consumption communications over a physical interconnect is described. In an embodiment, an input/output circuit includes a port to receive a transmission unit via an interconnect, a combining module coupled to the port to append at least one of a first and a second indicator to the transmission unit, a first adder module to generate the first indicator, indicating that the transmission unit is a starting transmission unit of a set of related transmission units, a second adder module to generate the second indicator, indicating that the starting transmission unit of the set of related transmission units has already been received, and logic to determine at least one of the start and end boundaries of the set of related transmission units.

Apparatus and method for reduced power consumption communications over a physical interconnect

A method and apparatus to monitor the performance of a processor. A performance specifier specifies a performance data corresponding to the performance. The performance data includes an event and an instruction causing the event. A tag generator is coupled to the performance specifier to generate a performance tag associated with the instruction. The performance tag is stored in a storage. A retirement performance monitor is coupled to the storage to extract the performance tag when the instruction is retired.

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Hillsboro, OR, United States of America

Selim Bilgin