Ess Technology, Inc.

Selim Bencuya

Richard Arthur Mann

Zeynep Toros

Jiafu Luo

Hiok-Nam Tay

Robert Lynn Blair

Erik Stauber

Max Safai

Alexandre G Grigoriev

Chi-Shao (Sergi) Lin

Heng Zhang

Richard Manrt

Miaohong Shi

There is provided a CMOS imager system for providing a viewable image having increased dynamic range including an image sensor including a number of sets of pixels. Each set of pixels is configured to receive one of a number of exposures and to generate image data corresponding to the received exposure in the interleaved mode. The image sensor is configured to operate in either an interleaved mode or a non-interleaved mode and to output the image data generated by each set of pixels as a frame of interleaved image data in the interleaved mode. The imager system further includes an interleaved image pipeline in communication with the image sensor, where the interleaved image pipeline is configured to receive the interleaved image data from the image sensor, combine the image data generated by each set of pixels corresponding to one of the exposures to form the viewable image.

CMOS imager system with interleaved readout for providing an image with increased dynamic range

An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.

Method and apparatus for controlling charge transfer in CMOS sensors with a transfer gate work function

Method and apparatus for controlling charge transfer in CMOS sensors with an implant by the transfer gate

Method and apparatus for proximate CMOS pixels

Method and apparatus for controlling charge transfer in CMOS sensors with a graded transfer-gate work-function

Method and apparatus for removing electrons from CMOS sensor photodetectors

Method for designing a CMOS sensor using parameters

Method and apparatus for varying a CMOS sensor control voltage

An exemplary CMOS image sensor comprises a reset transistor, a photodiode, reset drain voltage circuitry, and reset gate voltage circuitry. A cathode of the photodiode is connected to a source of the reset transistor, and an anode of the photodiode is connected to ground. The reset drain voltage circuitry is connected to a drain of the reset transistor, and the reset gate voltage circuitry is connected to a gate of the reset transistor. During an exemplary hard reset operation, the reset drain voltage circuitry supplies a first drain voltage to the drain of the reset transistor in accordance with a determined level of light for exposure, which is determined dynamically. According to another exemplary reset operation, a hard reset phase is immediately followed by a soft reset phase.

Method and system for resetting image sensors

An image sensor and method is provided to improve the measurement of a dark signal reference while substantially suppressing radiation charges that enter an active area of the image sensor from reaching a shielded dark signal detector. In one implementation, dark signal detector is shielded and separated from the active area to substantially reduce the radiation charges that reach the dark signal detector. In another implementation, the image sensor includes a radiation guard that is disposed between the active area and the shielded detector. When radiation or light is permitted to enter the active area, the guard when adequately biased attracts and collects radiated charges that may otherwise travel beyond the active area to reach the shielded detector and contaminate a measurement for the dark signal reference.

Suppressing radiation charges from reaching dark signal sensor

Image sensor with guard ring for suppressing radiation charges

Reducing reset noise in CMOS image sensors

An exemplary CMOS image sensor comprises a plurality of pixels arranged in an array. The plurality of pixels includes a first pixel proximate an optical center of the array, and a second pixel proximate a peripheral edge of the array. The CMOS image sensor further comprises a first metal interconnect segment associated with the first pixel situated in a first metal layer, and a second metal interconnect segment associated with the second pixel situated in the first metal layer. The second metal interconnect segment is shifted closer to the optical center of the array than the first metal interconnect segment so that the second metal interconnect segment approximately aligns with a principle ray angle incident the second pixel, thereby reducing pixel light shadowing.

CMOS image sensor arrangement with reduced pixel light shadowing

Growing community of inventors

Irvine, CA, United States of America

Selim Bencuya