University of South Florida

University of Rochester

Drexel University

Selcuk Kose

Huseyin Arslan

Berker Pekoz

Orhun Aras Uzun

Weize Yu

Mohammed Hafez

Eby G Friedman

Baris Taskin

Zekeriyya Esat Ankarali

Ragh Kuttappa

Modern integrated circuits have an increasing need for various levels of both supply voltage (V) and operating frequency (f) available at fine spatial and temporal granularity. This work introduces a solution that provides a number and quality of locally distributed V/f domains through FOPAC. Opportunistically sharing design resources and features between multi-phase voltage regulators (MPVRs) and resonant rotary clocks (ReRoCs) enabling i) the scalability to hundreds of domains, ii) fast switching times for both voltage and frequency, leading to temporal flexibility, and iii) locally distributed designs, leading to spatial flexibility.

Flexible on-chip power and clock

A system and method for frame structure compliant adaptive extensionless windowing that maximizes fair proportional network capacity in the download. Gains are provided by emulating the multipath multiple access channel to the base station to calculate almost-optimum transmitter windowing durations prior to transmission and using the variance of received symbols using different window durations to allow the user equipment nodes to estimate optimal receiver windowing durations without calculations requiring further knowledge about the network.

System and method for extensionless adaptive transmitter and receiver windowing

Methods and systems are provided for single false key-controlled (SFKC) aggressive voltage scaling (AVS) and multiple parallel false key controlled (MPFKC) AVS countermeasure systems. When a plaintext value is input into a cryptographic circuit for modification by a correct key, power supplied to the cryptographic circuit is scaled based on a result of the plaintext value modified by a false key or by a random number of parallel false keys, which occurs during every clock cycle. The scaling may be triggered when the operating frequency of the cryptographic circuit falls below a threshold, which indicates occurrence of a leakage power attack. A key that is detectable within a power trace of the scaled power provided to the cryptographic circuit, with a highest correlation coefficient relative to a known key, is a key other than the correct key. The MPFKC AVS technique also inhibits unriddling of the input power scaling scheme.

False key-controlled aggressive voltage scaling

Methods and systems are provided for a charge withholding converter reshuffling technique that decorrelates input power of a multi-phase switched capacitor (SC) voltage converter relative to the output power provided to a load. The load may be a cryptographic device. The technique provides a countermeasure against power analysis attacks. A controller including a first random number generator coupled to the stages of the SC voltage converter controls gating for charging a first subset of the stages. A controller including a second random number generator coupled the stages of the SC voltage converter controls gating for discharging a second subset the stages. A number of the switched capacitor stages maintain their charge beyond the switch period in which they are charged. The SC voltage converter withholds a random portion of input charge and delivers this charge to the load after a random time period.

System and method for switched-capacitor based side-channel countermeasures

Methods and systems are provided for a security adaptive (SA) voltage converter that receives input power from a power source and provides power to a cryptographic system. The SA voltage converter triggers countermeasures against leakage power analysis (LPA) attacks that slow down an operating frequency of the cryptographic circuit. When an LPA attack is detected, a discharging resistor sinks redundant current to alter the signature of load power dissipation of at the input to the SA voltage converter system. The SA voltage converter includes a converter reshuffling converter. The power dissipation induced by the discharging resistor, as measured at the input received from the power source, is scrambled by the SA voltage converter to increase noise inserted into the input power and to alter the power profile that is measured for the cryptographic circuit.

Security-adaptive voltage conversion as a lightweight counter measure against LPA attacks

A system and method for increasing the capacity of a Multiple-Input Multiple-Output (MIMO) system at desired user's locations and reducing the capacity at locations, other than that of the desired user, while also providing secrecy. Knowing the channel coefficient between each transmitter and receiver antenna pair at the transmitter, the method of the present invention calculates the artificial signal that minimizes the Euclidean distance between the desired and received data symbols if the precoding/combining matrix pair from the set that has the minimum Euclidean distance to the singular value decomposition (SVD) of the channel matrix is used for transmission and reception. The artificial signal may be fed to the precoder, instead of the actual desired data symbols, or may be transmitted directly to reduce computational complexity, power consumption and processing delay if the hardware configuration allows.

Using artificial signals to maximize capacity and secrecy of multiple-input multiple-output (MIMO) communication

System and method based upon an OFDM symbol, including a cyclic prefix (CP), that is received after being transmitted over a multiple access channel, wherein the CP is removed, and a Hann window is applied to the symbol. FFT is then applied to the Hann windowed symbol to obtain the frequency domain subcarriers. The pilot symbols are filtered accordingly to obtain Hann windowed pilots to estimate effective channel. Inter-carrier interference is calculated and removed.

OFDM reception under high adjacent channel interference while preserving frame structure

A system and method for adaptively utilizing transmitter windowing, receiver windowing and alignment signals for minimizing interference and maximizing capacity and energy efficiency based upon the received power ratios of links in adjacent bands of a cellular communication network.

Network-aware adjacent channel interference rejection and out of band emission suppression

Adaptive windowing of insufficient cyclic prefix (CP) for joint minimization of intersymbol interference (ISI) and adjacent channel interference (ACI) is provided. The proposed subcarrier specific windowing scheme improves the signal-to-interference ratio (SIR) even when the cyclic prefix (CP) is insufficient. Average optimal window lengths depend only on the power density profiles (PDPs), and although instantaneous optimal window lengths depend on users' channel impulse responses (CIRs), fluctuation is little. Therefore, subcarrier specific windowing outperforms fixed windowing, even with outdated window lengths in the case of powerful interferers.

Combined minimization of intersymbol interference (ISI) and adjacent channel interference (ACI)

Dynamic power management techniques and voltage converter architectures are described to provide a secure and efficient on-chip power delivery system. In aspects of the embodiments, converter-gating adaptively turns on and off individual stages of an interleaved switched-capacitor voltage converter based on workload information to improve voltage conversion efficiency. Converter-gating is further utilized as a countermeasure against side channel power analysis attacks by pseudo-randomly controlling converter activity. The embodiments also improve the response time of converters during transient load changes by adaptively configuring the conversion ratio of a switched capacitor (SC) voltage converter.

Secure converter-gating, reconfiguration, and regulation

Dynamic power management techniques and voltage converter architectures are described to provide a secure and efficient on-chip power delivery system. In aspects of the embodiments, converter-gating is used to adaptively turn individual interleaved switched-capacitor stages of a voltage converter on and off based on workload information to improve voltage conversion efficiency. Further, as a countermeasure against machine learning based differential power analysis attacks, for example, control signals provided to a number of the interleaved switched-capacitor stages are delayed to reduce the risk of low power trace entropy (PTE). A higher PTE value is maintained regardless of the phase difference between an attacker's sampling rate and the operating frequency, providing an additional layer of security.

Time delayed converter reshuffling

A system and method for adaptive activity management of on-chip voltage regulators based upon the workload information is provided to force each on-chip regulator to operate in its most power-efficient load current. In the proposed regulator-gating technique, regulators are adaptively turned ON when the current demand is high and turned OFF when the current demand is low to improve the voltage conversion efficiency. With the proposed regulator-gating system and method, the overall voltage conversion efficiency from the battery or off-chip power supply to the output of the on-chip voltage regulators experiences an approximately 3 times improvement over the prior art techniques.

System and method for distributed voltage regulator-gating

The present invention provides a digitally controlled, current starved, pulse width modulator (PWM). In the PWM of the present invention, the amount of current from the voltage source to the ring oscillator is controlled by the proposed header circuit. By changing the header current, the pulse width of the switching signal generated at the output of the ring oscillator is dynamically controlled, where the duty cycle can vary between 50% and 90%. A duty cycle to voltage converter is used to ensure the accuracy of the system under process, voltage, and temperature (PVT) variations. The proposed pulse width modulator is appropriate for dynamic voltage scaling systems due to the small on-chip area and high accuracy under process, voltage, and temperature variations.

Growing community of inventors

Tampa, FL, United States of America

Selcuk Kose