Motorola Corporation

Sejal N Chheda

Edward Outlaw Travis, Jr

Ruiqi Tian

Bradley Paul Smith

Tat-Kwan Edgar Yu

Aykut Dengi

Mark S Roberton

Alfred J Reich

Robert Elliott Boone

A semiconductor device and method of fabrication are disclosed. The device includes a first trench isolation region having an allowable tiling area and a second trench isolation region having an allowable tiling area, wherein the second trench isolation region is doped differently from the first trench isolation region. First tile structures disposed within first trench isolation region have a first set of design parameters while second tile structures disposed within the second trench isolation region have a second set of design parameters. At least one of the first set of design parameters is different from a corresponding design parameter in the second set of design parameters. The corresponding design parameters may include the density, size, pitch, shape, exclusion distance, minimum width, minimum length, and minimum area. The first trench isolation region may be doped with a first-type dopant and the second trench isolation region may be undoped or doped with an opposite second-type dopant.

Semiconductor tiling structure and method of formation

A method for forming an integrated circuit device having dummy features and the resulting structure are disclosed. One embodiment comprises a first active feature separated from a substantially smaller second active feature by a dummy-available region void of active features. Within the dummy-available region and in close proximity to the second active feature exists a dummy feature.

Method of forming an integrated circuit device using dummy features and structure thereof

Selective placement of polishing dummy feature patterns, rather than indiscriminate placement of polishing dummy feature patterns, is used. Both low frequency (hundreds of microns and larger) and high frequency (10 microns and less) of topography changes are examined. The polishing dummy feature patterns can be specifically tailored to a semiconductor device and polishing conditions used in forming the semiconductor device. When designing an integrated circuit, polishing effects for the active features can be predicted. After polishing dummy feature pattern(s) are placed into the layout, the planarity can be examined on a local level (a portion but not all of the device) and a more global level (all of the device, devices corresponding to a reticle field, or even an entire wafer).

Method for adding features to a design layout and process for designing a mask

A process for forming a masking database that includes defining a first feature level for the masking database corresponding to a first layer. The first feature level includes a first region with a first feature density and a second region with a second feature density that is substantially different from the first feature density. The process also includes defining a second feature level for the masking database corresponding to a second layer, wherein the second feature level is to be formed over a substrate after the first feature level has been formed over or within the substrate. A first feature within the second feature level will be formed within the first region, a second feature within the second feature level will be formed within the second region. The second layer will have a first thickness over the first layer within the first region and has a second thickness over the first layer within the second region. At least one of the first and second features is adjusted to at least partially compensate for a difference between the first and second thicknesses.

Selective sizing of features to compensate for resist thickness variations in semiconductor devices

At least one process-assist feature ( ) at or near a via location of a wiring structure ( ) within a semiconductor device is used to improve processing or processing margin during subsequent processing. For at least some of the embodiments of the present invention, the process-assist features feature ( ) help to make a flowable layer more uniform over via locations ( ). Typically, this can help in the formation of via openings. When a resist layer ( ) is formed over the process-assist features, the resist layer ( ) will have a more uniform thickness over most via locations within the device. When an insulating layer ( ) is formed over the via locations, the insulating layer ( ) will have a more uniform thickness over most via locations within the device. More control during resist exposure or via opening etching allow more process margin. The embodiments described herein illustrate the flexibility in placing process-assist features.

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Austin, TX, United States of America

Sejal N Chheda