Oki Electric Industry Co., Ltd.

Seizo Nakamura

Yuji Iguchi

Akinobu Kodama

A clock recovery circuit receives an input signal having an eye pattern and takes differences at certain intervals to generate a differential signal. A set of comparators detect timings at which the differential signal matches different levels, and generate pulse signals at these timings. A gate-signal generating circuit detects timing relationships among these pulse signals, and activates a gate signal when pulse sequences having certain timing relationships are detected. A delay circuit delays one of the pulse signals to create a delayed signal. A gate circuit outputs the delayed signal as a timing signal when the gate signal is active. A phase-locked loop generates a clock signal synchronized to the timing signal.

Clock recovery circuit employing delay-and-difference circuit and

An instantaneous phase detecting circuit for detecting the phase of a digital phase modulation wave signal which includes first and second logic circuits, first and second phase detecting circuits, and a third logic circuit. The first and second logic circuits receive the modulation wave signal, the first logic circuit receives a first carrier signal, and the second logic circuit receives a second carrier signal, the phase of the second carrier signal being delayed by a fixed period with respect to the phase of the first carrier signal. The first and second logic circuits generate first and second arithmetic outputs which are received by the first and second phase detecting circuits which detect the phases of the first and second arithmetic outputs to generate first and second detection output signals respectively. The third logic circuit receiving the first and second detection output signals and compares a periodic deviation of the first and second detection output signals to detect the phase of the modulation wave signal.

Instantaneous phase detecting circuit and clock recovery signal

A clock recovery circuit has at least two comparators that detect timings at which a digitally modulated signal crosses different levels, and generate level crossing signals at these timings. A classifying circuit classifies sequences of these level crossing signals and issues corresponding classification signals. A timing control circuit generates timing pulses from certain combinations of the level crossing signals and classification signals. A digital phase-locked loop outputs a clock signal synchronized to these timing pulses.

Clock recovery circuit with reduced jitter

A signal modulated by frequency-shift keying is input to a detector consisting of an instantaneous phase detection circuit that detects the instantaneous phase of the input signal, a differentiating circuit that differentiates the instantaneous phase to obtain the instantaneous frequency, and a baseband processing circuit that recovers clock and data signals from the instantaneous frequency. To detect the instantaneous phase, the instantaneous phase detection circuit compares the logic levels of the input signal and a clock signal, and filters the resulting bit stream with a digital low-pass filter. The detector consists entirely of digital circuits that are well suited for large-scale integration.

Frequency-shift-keying detector using digital circuits

In a device for producing a signal in synchronism with the phase of an input signal, a tapped delay timer produces a plurality of signals which have phases different from each other, a selection circuit selectively outputs the output signals of the tapped delay circuit, a frequency divider frequency-divides the output signal of the selection signal, a phase comparator compares the phases of the input digital signal and the output signal of the frequency divider, and a control circuit controls the selection circuit in accordance with the output of the phase comparator, so as to make the phase of the output signal of the frequency-divider to coincide with the input digital signal. A low-pass filter is provided to remove the hazard that is generated in the selection circuit. A waveform shaping circuit is provided to shape the waveform of the output signal of the low-pass filter into rectangular waveform.

High-speed digital PLL device

An apparatus and a method for adaptively discriminating high and low levels of data signals to be demodulated into digital signals, which includes a reference signal generator, first and second sample and hold circuits, a discrimination signal generator, a timing signal generator and a discriminator. The first sample and hold circuit samples data signals at first discrete times at which the discriminator detects a high level of the data signal in relation to a discrimination level, and outputs a first sample signal whose level depends upon the level of the data signals at the first discrete times. Similarly, the second sample and hold circuit samples a low level of the data signals and outputs a second sample signal whose level depends upon the level of the data signals at the second discrete times. The apparatus further includes a signal generator which generates an average of an absolute value of the levels of the sample signal first and that of the second sample signal and a further signal generator which generates an inversion of the average signal. An additional signal generator has a low-pass filter and selector to selectively apply one of the average and inversion signals to the low-pass filter. The selector applies the inversion signal when the discriminator detects that the high level of the data signals has been inputted, otherwise, it applies the average signal. The output of the low-pass filter is a reference signal formed of a composite of the inversion and average signals. The reference signal is applied to the discrimination signal generator which produces the discrimination level so as to adjust the level of the discrimination level in proportion to the level reference signal.

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Tokyo, Japan

Seizo Nakamura