Sharp Kabushiki Kaisha Corporation

Other

Seizo Kakimoto

Hiroshi Iwata

Masayuki Nakano

Akihide Shibata

Kouichiro Adachi

Nobutoshi Arai

Katsuji Iguchi

Toshimasa Matsuoka

Masayoshi Koba

Jun Kudo

Shigeki Hayashida

Satoshi Morishita

Naoyuki Shinmura

Kouichirou Adachi

Akira Sakai

Tatsuya Morioka

Yoshihiko Tani

Toshihiko Fukushima

Tsukasa Doi

Takayuki Ogura

Sung T Ahn

Takashi Fukushima

Tomohisa Okuno

Shin Shimizu

Hiroshi Kotaki

Yukio Yasuda

Shigeaki Zaima

Masayuki Lm Narayasuraginomichi 201 Nakano

A memory function body has a medium interposed between a first conductor (e.g., a conductive substrate) and a second conductor (e.g., an electrode) and consisting of a first material (e.g., silicon oxide or silicon nitride). The medium contains particles. Each particle is covered with a second material (e.g., silver oxide) and formed of a third material (e.g., silver). The second material functions as a barrier against passage of electric charges, and the third material has a function of retaining electric charges. The third material is introduced into the medium by, for example, a negative ion implantation method.

Memory function body, particle forming method therefor and, memory device, semiconductor device, and electronic equipment having the memory function body

A resistance-changing function body includes an object made of a first substance and interposed between a first electrode and a second electrode, and a plurality of particles made of a second substance and arranged within the object so that an electrical resistance between the first electrode and the second electrode is changed before and after application of a specified voltage to between the first electrode and the second electrode. The first substance makes an electrical barrier against the second substance. With this constitution, by applying a specified voltage to between the first electrode and the second electrode, the electrical resistance can be changed depending on a state of the particles made of the second substance. Also, by virtue of a simple structure, a resistance-changing function body of small size is provided with low cost.

Memory device including resistance-changing function body

The yield of a semiconductor device is improved which has a large-scale logic circuit or which has both a logic circuit and a memory. A basic circuit block is provided with an input/output circuit. A transmission line and a branch line connect the input/output circuits so that information can be exchanged through the input/output circuits between one basic circuit block and another basic circuit block. The memory in each basic circuit block or in each input/output circuit can be programmed from the outside to designate the destination of a signal. By thus changing the program in the memory, the transmission destination of a signal can be changed to give various functions efficiently with a limited circuit scale. Moreover, if a basic circuit block fails another basic circuit block substitutes for it to improve the yield drastically.

Semiconductor device

There is provided a semiconductor storage device capable of high integration. On a top surface of a semiconductor substrate, a plurality of device isolation regions () each extending and meandering in a lateral direction are formed so as to be arrayed with respect to a longitudinal direction, by which active regions are defined between neighboring ones of the device isolation regions (), respectively. Dopant diffusion regions (source or drain) are formed at individual turnover portions (corresponding to contacts (), ()), respectively, of the meanders within the active regions. A plurality of word lines () extending straight in the longitudinal direction run on the channel regions within the active regions via a film having memory function, respectively. A first bit line () extending straight in the lateral direction runs on the dopant diffusion region (corresponding to contact ()) provided at a crest-side turnover portion. A second bit line () extending straight in the lateral direction runs on the dopant diffusion region (corresponding to contact ()) provided at a trough-side turnover portion.

Semiconductor storage device and semiconductor integrated circuit

A semiconductor devicecomprises a semiconductor substrateincluding an isolation regionand an active region, a gate electrodeprovided on the active regionvia a gate insulating film, part of a side of the gate electrodebeing covered with a gate electrode side wall insulating film, and a source regionand a drain regionprovided on opposite sides of the gate electrodevia the gate electrode side wall insulating film. At least one of the source regionand the drain regionhas a second surface for contacting a contact conductor. The second surface is tilted with respect to a first surface A&#x2013;A'. An angle between the second surface and a surface of the isolation region is 80 degrees or less.

Semiconductor device, method for producing the same, and information processing apparatus

There is provided a semiconductor device including DTMOS and a substrate variable-bias transistor and a portable electronic device both operable with reduced power consumption. N-type deep well regions are formed in one P-type semiconductor substrate. The N-type deep well regions are electrically isolated by the P-type semiconductor substrate. Over the N-type deep well regions, a P-type deep well region and a P-type shallow well region are formed to fabricate an N-type substrate variable-bias transistor. Over the N-type deep well region, an N-type shallow well region is formed to fabricate a P-type substrate variable-bias transistor. Further a P-type DTMOS and an N-type DTMOD are fabricated.

Semiconductor device having device isolation region and portable electronic device

A memory film operable at a low voltage and a method of manufacturing the memory film; the method, comprising the steps of forming a first insulation film () on a semiconductor substrate () forming a first electrode, forming a first conductor film () on the first insulation film (), forming a second insulation film (B) on the surface of the first conductor film (), forming a third insulation film containing conductor particulates () on the second insulation film (B), and forming a second conductor film forming a second electrode on the third insulation film.

Memory film, method of manufacturing the memory film, memory element, semiconductor storage device, semiconductor integrated circuit, and portable electronic equipment

A memory function body, which includes a plurality of silver particlescovered with silver oxide, is interposed between a first electrodeand a second electrode. A magnitude of a current through the memory function bodychanges on applying a prescribed voltage between the first electrodeand the second electrode, and a storage state is discriminated according to the magnitude of the current. The silver particles, which capture electric charges, are covered with the silver oxidethat serves as a barrier against the passage of electric charges, and therefore, the memory function bodycan stably retain electric charges at the normal temperature.

Resistance-changing function body, memory element, manufacturing method therefor, memory device, semiconductor device and electronic equipment

There is provided a semiconductor device of low power consumption and high reliability having DTMOS' and substrate-bias variable transistors, and portable electronic equipment using the semiconductor device. On a semiconductor substrate (), trilayer well regions () are formed, and DTMOS' () and substrate-bias variable transistors () are provided in the shallow well regions (). Large-width device isolation regions () are provided at boundaries forming PNP, NPN or NPNP structures, where a small-width device isolation region () is provided on condition that well regions on both sides are of an identical conductive type. Thus, a plurality of well regions of individual conductive types where substrate-bias variable transistors () of individual conductive types are provided can be made electrically independent of one another, allowing the power consumption to be reduced. Besides, the latch-up phenomenon can be suppressed.

Semiconductor device and portable electronic apparatus

A semiconductor device having a two-layer well structure and a small margin required at the boundary of a well region and comprising a substrate-bias variable transistor and a DTMOS. Field effect transistors () are formed on a P-type shallow well region (). The depth of a shallow device isolation region () on the P-type shallow well region () is less than the depth of the junction between an N-type deep well region () and the P-type shallow well region (). Therefore the field effect transistors () share the P-type shallow well region (). The P-type shallow well regions () independently of each other are easily formed since they are isolated from each other by a deep device isolation region () and the N-type deep well region ().

Semiconductor device and its production method

A semiconductor device comprises a semiconductor substrate including an isolation region and an active region a gate electrode provided on the active region via a gate insulating film part of a side of the gate electrode being covered with a gate electrode side wall insulating film and a source region and a drain region provided on opposite sides of the gate electrode via the gate electrode side wall insulating film At least one of the source region and the drain region has a second surface for contacting a contact conductor. The second surface is tilted with respect to a first surface A-A&prime;. An angle between the second surface and a surface of the isolation region is 80 degrees or less.

Semiconductor device, method of manufacture thereof, and information processing device

A semiconductor device with dynamic threshold transistors includes a complex element isolation region composed of a shallow element isolation region made of shallow trench isolation and deep element isolation regions provided on both sides of the shallow element isolation region. Since the shallow element isolation region is made of the shallow trench isolation, Bird's beak in the shallow element isolation region is small. This prevents off leakage failure due to stress caused by the bird's beak. The deep element isolation region has an approximately constant width which allows the complex element isolation region to be wide.

Semiconductor device having dynamic threshold transistors and element isolation region and fabrication method thereof

A semiconductor device according to the present invention includes a semiconductor substrate; device isolation regions provided in the semiconductor substrate; a first conductivity type semiconductor layer provided between the device isolation regions; a gate insulating layer provided on an active region of the first conductivity type semiconductor layer; a gate electrode provided on the gate insulating layer; gate electrode side wall insulating layers provided on side walls of the gate electrode; and second conductivity type semiconductor layers provided adjacent to the gate electrode side wall insulating layers so as to cover a portion of the corresponding device isolation region, the second conductivity type semiconductor layers acting as a source region and/or a drain region. The gate electrode and the first conductivity type semiconductor layer are electrically connected to each other. The second conductivity type semiconductor layers are provided above the first conductivity type semiconductor layer and have a thickness which gradually increases from the device isolation region toward the gate electrode.

Growing community of inventors

Nara, Japan

Seizo Kakimoto