Sanyo Electric Co., Ltd.

Seiya Ota

Yuichi Kanai

Yoshihiro Hori

Yutaka Shimizu

Toshiaki Hioki

Miwa Kanamori

Kazuya Ogawa

Tohru Kawabata

Masaya Okumura

Megumi Makino

Jiro Yokoyama

Yosuke Mizutani

There are described a data recording system, a data recording method, and a recording medium, all of which are directed to enabling easy editing of AV data without involvement of duplication of the AV data, as well as to eliminating a necessity for an additional data recording region. In the recording system, at the time of recording of primary data, there is prepared an original file which stores link data formed by arranging in sequence address data for reproduction purposes stored in a recording region on a recording medium. Further, through editing of the original file, there is prepared a virtual file which stores link data formed by arranging in sequence address data for reproduction purposes stored in the recording region on the recording medium. The data are reproduced according to these files.

Information recorder, recording method, and recording media

A portable telephone set capable of recognizing a call during music replay is disclosed. This portable telephone set comprises talking means and music replay means, and posts a call when receiving the same during music replay by the music replay means. Thus, the call can be recognized during the music replay.

Portable telephone set

A data delivery server () includes a download server (), and a mobile telephone () is connected to the download server () via an Internet (), a mobile telephone network (), and a radio base station (). The mobile telephone () is capable of downloading desired music data from the data delivery server (). More specifically, a menu server () determines one access point where traffic is not congested based on a connection situation to the access point of the download server (), and transmits to the mobile telephone () download information including a content ID which recognizes a determined access point and the desired music data. Therefore, the mobile telephone () is capable of downloading the music data by connecting it to the download server () from the access point where traffic is not congested based on the download information. Thus, a required time for downloading cannot be longer than necessary.

Data distribution server, terminal, and data distribution system

A video signal processing circuit includes an input processor configured to modify an input video signal in accordance with image magnification data and a buffer memory for storing the modified video signal. The processing unit also includes a write control unit configured to control a write function to the buffer memory by generating a write control signal in accordance with the image magnification data. The write control unit includes a calculating circuit configured to calculate image size data on the basis of the write control signal in response to a change in the image magnification data. The write control unit also includes an inhibition circuit configured to inhibit the write function to the buffer memory at least while the calculation circuit calculates the image size data. The processing unit further includes a read control unit for controlling reading from the buffer memory in accordance with the calculated image size data. A method of processing a video signal also is disclosed.

Video signal processing

A video signal processing circuit uses a buffer memory for reducing or expanding video signals in the generation of child images to be displayed within a display window. Image size data, stored in a header within the buffer memory, and a reduced video signal are prevented from representing different image reduction ratios which might otherwise occur when the reduction ratio is changed. At the time of changing the reduction ratio, image size data SIZ are calculated from a write enable signal based on reduction ratio data K, for a one-field period just after the change by an input video clock generator 22. The calculated image size data are written to a header together with a reduced video signal in a field memory 2, and a flag bit SP indicating the change in the reduction ratio is also written to the header for the one-field period just after the change. When data are read from the buffer memory, the flag bit SP is detected by a display video clock generator 23 to mute a video signal output when there is a likelihood of displaying distorted data. On the other hand, writing to the field memory 2 is inhibited for the one-field period just after the change in the image magnification data so that the muting period of the video signal output can be shortened.

Video signal processing circuit inhibiting display of distorted images

A write clock signal and a write select signal are outputted from an input video clock generator, a read clock signal and a read select signal are outputted from a display video clock generator, either of first and second field memories is selected as the write memory or the read memory in compliance with the signal level of the respective select signal and writing is carried out in the selected write memory once a predetermined time has elapsed following inversion of the write select signal. When reading has commenced from the first and second buffer memory, a match is detected between the signal levels of the write select signal and the read select signal at each field or at each frame and writing and thus reading address passing is predicted.

Video signal processing circuit for monitoring address passing between

A video signal converter comprising a frequency setting circuit, a first clock generator, a second clock generator, an analog-to-digital converter, a line conversion ratio setting circuit, a number of scanning lines converter, a frame memory, a writing controller, a reading controller and a digital-to-analog converter is disclosed. The frequency setting circuit sets a first frequency Fi which satisfies a formula: Fi.ltoreq.(To.times.Fo)/Ti, where Ti is a horizontal scanning period of a first analog video signal, To is a horizontal scanning period of a second analog video signal and Fo is a second frequency. The line conversion ratio setting circuit sets a line conversion ratio R which satisfies an equation: R=m/k, based on a width-to-height ratio 1/m of each pixel of the first digital video data and a width-to-height ratio 1/k of each pixel of second digital video data. The number of scanning lines converter converts any digital video data having a first number of scanning lines to varied digital video data having a second number of scanning lines, the second number of scanning lines being R-times the first number of scanning lines. The writing controller memorizes the first digital video data into the memory in synchronization with the first clock of the first frequency Fi. The reading controller reads the first digital video data from the memory in synchronization with the second clock of the second frequency Fo to generate the second digital video data.

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Aichi, Japan

Seiya Ota