Kabushiki Kaisha Toshiba

Toshiba Microelectronics Corporation

Seishi Irie

Takahiro Sato

Toshiyuki Kondo

Tomoya Osaki

Katsumasa Hayashi

A semiconductor memory device includes a cell array having matrix-like arrayed plural SRAMs on a semiconductor substrate having an N-well and P-well. The N-well and the P-well are isolated from each other with an isolation region each having a shallow trench structure. Each memory cell includes two CMOS inverter circuits having input and output nodes making a cross-coupled connection. First and second capacitors are connected between each gate node of two CMOS inverter circuits and the N-well and/or N-well.

Semiconductor memory device having a shallow trench isolation structure

An object of the present invention is to provide a semiconductor device where a metal wiring pattern is improved in order to prevent photoresist foaming from occurring without employing a special process, even if a protective layer void occur in a wire to wire space in the metal wire, and an arrangement method for a semiconductor device pattern. To achieve the above object, the present invention provides a semiconductor device comprising a first wiring layer and a second wiring layer arranged in a row on a semiconductor substrate, and a insulating layer on the first wiring layer and the second wiring layer so that a first portion of the insulating layer on the first wiring layer is prevented from touching a second portion of the insulating layer on the second wiring layer.

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Yokohama, Japan

Seishi Irie