Fujitsu Corporation

Seiko Osaki

Koji Abe

In a method of designing a layout of an LSI chip, which LSI chip has boundary scan registers, after arranging I/O cells and before arranging an internal logic circuit and the like, I/O connection boundary scan registers are preferentially arranged in empty regions of the I/O cells. Output I/O control boundary scan registers are arranged at intermediate points between the I/O connection boundary scan registers, respectively, or a chip side closer to the intermediate points. Thereafter, before arranging cells constituting other circuits and creating a wiring pattern, buffer cells are inserted into nets of test signals to the boundary scan register led to a test control circuit.

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Kawasaki, Japan

Seiko Osaki