International Business Machines Corporation

Halo Lsi, Inc.

Matsushita Electric Industrial Co., Ltd.

Halo Lsi Design Device Technology, Inc.

Other

New Halo, Inc.

Halo Lsi Device & Design Technology, Inc.

Halo Lsi Design and Device Technologies, Inc.

Halo, Inc.

Gumbo Logic, Inc.

Aalo Lsi Design & Device Technology, Inc.

Halo Lsi Design and Devices Technologies Inc.

Seiki Ogura

Tomoko Ogura

Tomoya Saito

Nori Ogura

Nivo Rovedo

Louis L Hsu

Kimihiro Satoh

Shinji Odanaka

Joseph F Shepard

Yutaka Hayashi

Chang-Ming Hsieh

Hiromasa Fujimoto

Junichi Kato

Atsushi Hori

Fumihiko Noro

Robert C Wong

Jacob Riseman

Kaori Akamatsu

Masataka Kusumi

Joyce E Acocella

Carol Galli

Nobuyo Sugiyama

Akihiro Kamada

Paul J Tsang

Taqi Nasser Buti

Christopher Frank Codella

Anthony J Dally

Yoshitaka Baba

Pascal R Tannhof

Pierre B Mollier

Ronald N Schulz

Toshio Mii

Shah Akbar

Patricia L Kroesen

Tomoko Iwasaki

Jack Allan Mandelman

Roy E Scheuerlein

Karen A Nummy

Klaus D Beyer

Michael Daniel Monkowski

James P Peng

Lyndon Ronald Logan

Gerard Boudon

Myriam Combes

Karanam Balasubramanyam

George W Doerre

Dominique P Bonneau

Ki-Tae Park

Dominique M Omet

Eric Mendel

Takaaki Aoki

James S Makris

Mark E Jost

Franck Wallart

Ryo Igarashi

Yutaba Hayashi

Paul S Kim

Paul Evrenidis

Kumihiro Satoh

A charge trap type of memory having a memory channel with vertical and possibly horizontal components is described. The invention includes a new operation method of simultaneous hole and electron injection operation for high speed and high reliability non-volatile memories, as well as high-density non-volatile memories. Array implementations for high-density memory arrays and high-speed memory arrays and their fabrication methods are also described.

High density vertical structure nitride flash memory

Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits.

Complementary reference method for high reliability trap-type non-volatile memory

The present invention provides a novel read method of twin MONOS metal bit or diffusion bit structure for high-speed application. In a first embodiment of the present invention, the alternative control gates are set at the same voltage. In a second embodiment of the present invention, all the control gates are set at the operational voltage from the beginning. In both embodiments, the bit line and word gate are used to address the selected memory cell.teh

High speed operation method for twin MONOS metal bit array

A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

Trap-charge non-volatile switch connector for programmable logic

The present invention provides a novel operational method of twin MONOS metal bit or diffusion bit structure for high-speed application. In a first embodiment of the present invention, the alternative control gates are set at the same voltage. In a second embodiment of the present invention, all the control gates are set at the operational voltage from the beginning. In both embodiments, the bit line and word gate are used to address the selected memory cell.

A reference circuit is described for creating a reference signal using a twin MONOS memory cell. A first portion of the twin MONOS memory cell connects to a charged and floating bit line a current source formed in a second portion of the twin MONOS cell that discharges the charged bit line to form a reference signal for a sense amplifier. The sense amplifier compares the reference signal to a signal from a selected memory cell upon which memory operations are being performed comprising read, erase verify and program verify.

Referencing scheme for trap memory

The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

Twin insulator charge storage device operation and its fabrication method

Growing community of inventors

Wappingers Falls, NY, United States of America

Seiki Ogura