Matsushita Electric Industrial Co., Ltd.

Seijirou Kojima

Hiroyuki Tsujikawa

Kenji Shimazaki

Shouzou Hirano

Kasumi Hamaguchi

Hidetoshi Narahara

In a gate-level logic simulation, a change in electric current is calculated from event informationoutput from a logic simulatorthrough use of a current waveform calculation section. The thus-calculated change in current is subjected to FFT processing through use of an FFT processing section, thereby determining a frequency characteristic of EMI and enabling EMI analysis.

Method of analyzing electromagnetic interference

In contrast with a known dynamic gate-level simulation method, a method of analyzing electromagnetic interference (an EMI analysis method) according to the present invention enables estimation of EMI noise, by means of calculating signal propagation of each node through use of the signal propagation probability technique, and calculating variation time of each node through use of 'the Static timing analysis technique'. In short, the present invention is characterized in calculating a frequency characteristic from the relationship between toggle probability of each node and delay in each node.

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Kyoto, Japan

Seijirou Kojima