Sharp Kabushiki Kaisha Corporation

Seijirou Gyouten

Yuhichiroh Murakami

Shige Furuta

Yasushi Sasaki

Hajime Washio

Sachio Tsujino

Shuji Nishi

Etsuo Yamamoto

Eiji Matsuda

Satoshi Horiuchi

Makoto Yokoyama

Shunsuke Hayashi

Takahiro Yamaguchi

Yoshihiro Asai

Yuichiro Murakami

Naoyuki Tajima

Yoshinori Ogawa

Noboru Matsuda

Shunichi Murahashi

Shinya Takahashi

Seiya Kawamorita

Isao Ogasawara

Junichi Morinaga

Shigeto Yoshida

Shinsaku Shimizu

Yasunori Chikawa

Keiichi Ina

Shigeki Tamai

Takehiko Kawamura

Takuya Hachida

Mamoru Onda

Hoh Riku

Shinji Matsubara

Yuhiehiroh Murakami

A circuit substrate includes a substrate portion having a variable-external-shape portion; a circuit portion, having a configuration in which circuit blocks adjacent to each other in a first direction; a plurality of trunk wiring lines bent along the circuit blocks displaced with respect to each other in a second direction; and a plurality of branch wiring lines, wherein the plurality of trunk wiring lines include a first trunk wiring line and a second trunk wiring line, and among the plurality of branch wiring lines, a plurality of branch wiring lines connected to a plurality of unit circuits constituting a center-side circuit block include at least a first branch wiring line connected to the first trunk wiring line and a second branch wiring line connected to the second trunk wiring line and disposed farther than the first branch wiring line from a end-side circuit block in the first direction.

Circuit substrate and display device

A unit circuit of a shift register includes an output transistor whose control terminal is connected to a first node, first and second set transistors, first and second reset transistors, a control signal generating circuit that generates a control signal that changes to an on level when a first clock signal changes to an on level while the potential of the first node is at an off level, and that outputs the generated control signal to the unit circuits at a preceding stage and a next stage, a transistor that applies an off-level potential to the first node based on a control signal output from the unit circuit at the preceding stage, and a transistor that applies an off-level potential to the first node based on a control signal output from the unit circuit at the next stage.

Shift register and display device provided with the same

A plurality of circuit portions include a central side circuit portion connected to at least a central side-wiring line lead-out portion among a plurality of wiring line lead-out portions, and an end side circuit portion that is connected to at least an end side-wiring line lead-out portion among the plurality of wiring line lead-out portions, is also located on an end side in a first direction being an extending direction of a central side-outer shape portion having a linear shape with respect to the central side circuit portion, and is configured such that a dimension in a second direction being a direction in which the plurality of circuit portions and a central side region are aligned is smaller than that of the central side circuit portion.

Circuit substrate and display panel

A gate driving circuit includes circuits each provided in such a manner as to, as a scanning signal, select a single clock pulse of a clock signal and output the clock pulse. The circuits each include: a transistor for outputting a scanning signal; a transistor for controlling an electric potential of a gate of the transistor so that the electric potential of the gate is at a low level; a transistor for, while the transistor is not outputting the scanning signal, controlling an electric potential of a gate of the transistor so that the electric potential of the gate is at a high level; and a transistor for, while the transistor is not in operation during a period during which an operation of the selection circuit is paused, controlling the electric potential of the gate of the transistor so that the electric potential becomes high.

Display driving device and display device having electric potential controlling circuitry

A display device has a display panel including gate lines, a driving circuit, and an auxiliary circuit corresponding to each gate lines. To the driving circuit and the auxiliary circuit, one driving signal of M-phase driving signals (M&#x2265;4) having selection potential and non-selection potential, is supplied. The driving circuit outputs the driving signal to a corresponding gate line. A selection period for the gate line includes a pre-charging period and a main charging period, and the main charging period overlaps with the pre-charging period for the adjacent gate line. The auxiliary circuit is driven during the main charging period for the corresponding gate line and during the main charging period for the next gate line. The auxiliary circuit outputs the selection potential during the main charging period for the corresponding gate line, and outputs the non-selection potential during the main charging period for the next gate line.

Display device

Provided is a technique of suppressing display defects such as flicker, without limiting the arrangement of data lines, in a liquid crystal display device having a display area in a non-rectangular shape. A liquid crystal display device includes an active matrix substrate 10, a counter substrate, and a liquid crystal layer. The active matrix substrate 10 includes a plurality of gate lines 11, and a plurality of data lines 12. In each of pixels defined by the gate lines 11 and the data lines 12, a pixel electrode 14 is arranged, and in a display area R, common electrodes 15 are provided. Outside the display area R, capacitance-generating parts C that generate capacitances between some gate lines 11 among the plurality of gate lines 11 and the common electrode are provided. The some gate lines 11 have lengths smaller than the gate lines having the maximum length, and intersect with some data lines 12 among the plurality of data lines 12. The capacitance-generating parts C are provided in such a manner that at least one capacitance-generating part C is provided with respect to one of the some gate lines 11.

Liquid crystal display device

A display device is provided which is capable of preventing a malfunction and carrying out a common reverse drive without increasing electric power consumption. The display driver (a) supplies a voltage of a common electrode, whose a polarity is determined in accordance with (i) an oscillation circuit output signal (OCOUT) which is transmitted via a first wire different from a second wire used during a serial transmission and (ii) a SCS signal and (b) controls a reverse timing of the polarity of the voltage of the common electrode in accordance with the oscillation circuit output signal (OCOUT) and the SCS signal.

Display device and electrical apparatus

A shift register is disclosed which includes, at respective stages, unit circuits () each including (i) a flip-flop () including first and second CMOS circuits and (ii) a signal generation circuit () for generating an output signal (SROUTk) for the current stage with use of an output (Q, QB) of the flip-flop (), the shift register including a floating control circuit () between a gate terminal of an output transistor (Tr) of the signal generation circuit () and a Q terminal. This makes it possible to reduce a circuit scale of a display driving circuit without causing a shift register to malfunction.

Shift register, display drive circuit, display panel, and display device

A retention circuit () corresponding to each stage of a shift register is configured such that, when SROUT(k&#x2212;1) is active, an input terminal of an inverter (INV) and an output terminal of an inverter (INV) are electrically connected to each other and an output terminal of the inverter (INV) and an input terminal of the inverter (INV) are connected to each other. This makes it possible to reduce a circuit scale of a display driving circuit without causing any malfunction of the display driving circuit.

Display drive circuit, display panel, and display device

This display device has a demultiplexer () formed on a liquid crystal panel, the demultiplexer including three switching elements SWto SWfor time-division drive, which are connected to video signal lines SLto SL. Here, the number of switching control signal lines for transmitting switching control signals GSto GSto be provided to switching elements coupled to the video signal lines is six, which is twice the number of time divisions, and switching control signals (e.g., GSand GS) with the same timing are individually transmitted by two switching control signal lines, so that the number of switching elements to be coupled to the switching control signal lines as loads can be halved, resulting in reduced waveform rounding of the control signals.

Display device and method of driving the same

A display device employing CC driving switches from (i) a first mode in which to carry out a display by converting resolution of a video signal by a factor of 2 in a column-wise direction to (ii) a second mode in which to carry out a display at the resolution of the video signal. During the first mode, signal potentials having the same polarity and the same gray scale are supplied to pixel electrodes included in respective two pixels that correspond to two adjacent scanning signal lines and that are adjacent to each other in the column-wise direction, and a direction of change in the signal potentials written to the pixel electrodes varies every two adjacent rows (2-line inversion driving). During the second mode, the direction of change in the signal potentials written to the pixel electrodes lines varies every single row (1-line inversion driving).

Display driving circuit, display device, and display driving method

A flip-flop circuit () includes: an input transistor (Tr) having a gate terminal thereof connected to an SB terminal, a source terminal thereof connected to an RB terminal, and a drain terminal thereof connected to a first CMOS circuit and a second CMOS circuit; a power supply (VSS) which is connected to the first CMOS circuit or the second CMOS circuit and, when an SB signal is turned to be active, is connected to the RB terminal; and a regulator circuit (RC). With the arrangement, a compact flip-flop and a compact shift register employing the flip-flop are provided, without causing malfunction of the flip-flop and the shift register.

Flip-flop, shift register, display panel, and display device

A memory-type liquid crystal display device includes transistors (N, N), retention electrodes (MRY), refresh output control sections (RS), and capacitors (Cb). In a data retention period, an electric potential of each of the retention electrodes (MRY) is changed via a corresponding one of the capacitors (Cb) by changing an electric potential level of a retention capacitor wire signal that is supplied to a corresponding CS line (CSL(i)). Each of the refresh output control sections (RS) receives the electric potential thus changed of a corresponding one of the retention electrodes (MRY) via the input section and controls an electric potential of a corresponding pixel electrode (PIX) in accordance with the electric potential thus changed.

Liquid crystal display device and method for driving same

A shift register includes a plurality of stages of unit circuits each including a flip-flop. Each of the unit circuits generates, by obtaining a sync signal in accordance with an output from the flip-flop, an output signal. The flip-flop includes a first switch and a second switch and a latch circuit for latching a signal supplied thereto and outputting the signal as the output from the flip-flop. A first shift direction signal is supplied to the latch circuit via the first switch, and the second shift direction signal is supplied to the latch circuit via the second switch. In each unit circuit other than those of the first and last stages, an output signal from a previous stage is supplied to a control terminal of the first switch, and an output signal from a subsequent stage is supplied to a control terminal of the second switch.

Shift register, signal line drive circuit, liquid crystal display device

An embodiment of the present invention switches, in a display driving circuit of a liquid crystal display device which carries out CC driving, between a two-line reversal driving mode in which a polarity of a data signal supplied to a source line is reversed every two horizontal scanning periods and a one-line reversal driving mode in which a polarity of a data signal supplied to a source line is reversed every one horizontal scanning period. In at least one example embodiment, a polarity signal reverses its polarity every two horizontal scanning periods in the two-line reversal driving mode, and reverses its polarity every one horizontal scanning period in the one-line reversal driving mode.

Growing community of inventors

Osaka, Japan

Seijirou Gyouten