Matsushita Electric Industrial Co., Ltd.

Seiji Yamaguchi

Tadashi Matsuyo

Masaru Moro

Munehisa Ikoma

Tsuguyasu Hatsuda

Eisuke Ichinohe

Masahiro Kimura

Yoshinori Toyoguchi

Osamu Yamamoto

Kohei Suzuki

Hidenori Kitamura

Kazuki Ninomiya

Hirokazu Yonezawa

Katsunori Komori

Shuji Abe

Hiroshi Kawakami

Kazuhiko Tsuji

Koutarou Hirai

Hideo Okubo

Hidetoshi Imai

Tadao Kimura

Yasuhiro Tomita

Shinichi Yuasa

Yoshitaka Murata

Nobuhiro Hayashi

Toru Kakiage

Hiroshi Mori

Joji Katsura

Kazuhisa Morishita

Yuichi Shimizu

Tomohiro Kurozumi

Haruo Terai

Takaaki Ogawa

Toru Odachi

Saburo Kajikawa

Shinji Kondoh

Tomonori Kato

Osamu Taketoshi

Masaki Shibuya

Toshiichiro Tanaka

Tomomi Mitani

Ichirou Matsuo

Shiro Yoshioka

Hiroyuki Uratani

Tsuyoshi Tokuda

Yumiko Hara

Tsuyoshi Nishimura

Masakuni Soejima

Ryohei Yoshida

Masashi Okushima

Akihisa Oka

Toshifumi Miyahara

Hirokazu Nagaoka

Yasushi Kondo

Yoshihiro Taniguchi

Kouichi Fujita

Haruka Ishikawa

Yoshiki Kuroki

Yoshiaki Onishi

Saburou Kajikawa

Ayako Tanaka

Johji Katsura

A vacuum cleaner includes a first dirt separation unit and a second dirt separation unit. The first dirt separation unit has a first inlet port through which a suction air stream including dirt particles is introduced thereinto, and the second dirt separation unit has a second inlet port through which the air stream introduced into the first dirt separation unit is introduced into the second dirt separation. The first and the second inlet port are disposed such that they are not registered with each other. Accordingly, the dirt particles suctioned are separated in two stages, thereby decreasing the possibility of occlusion of a filter and rapid deterioration of a suction force.

Vacuum cleaner

A vacuum cleaner includes an electric blower for generating a suction air flow, a suction head in communication with the electric blower for drawing in dirt, a filter bag communication with the electric blower for capturing and collecting dirt, an exhaust unit for discharging exhaust air from the electric blower to atmosphere, and an ion generator for generating negative ions and/or positive ions. The ion generator is placed between the suction head and the filter bag.

Vacuum cleaner having an ion generator

An electric blower includes a motor unit having a stator and a rotor, a fan unit having an impeller attached to an output shaft of the rotor, and a circuit unit having a heat-generating component for controlling electric power to the motor unit. The circuit unit is arranged in an airflow path of air expelled from an outer periphery of the impeller toward the stator and the rotor of the motor unit. The air suctioned by rotation of the impeller cools the heat-generating component in the circuit unit before cooling the stator and the rotor.

Electric blower and electric cleaner with an air cooled power device situated between the impeller and motor

Disclosed is a hydrogen storage alloy electrode for use in alkaline storage batteries that can reduce internal resistance of the battery and can give an excellent output characteristic and a long cycle life to the battery. The electrode comprises an AB,-type hydrogen storage alloy powder, a yttrium compound and a compound of a light rare earth element. The total content of the yttrium compound and the compound of a light rare earth element is in a range of 0.5 to 2.0 parts by weight per 100 parts by weight of hydrogen storage alloy powder. Preferable ratios of the yttrium compound and the compound of a light rare earth element selected from La, Ce, Pr and Nd are, respectively, 60 wt % or more and 7 wt % or less in the total amount of the yttrium compound and the compound of the light rare earth element.

Hydrogen storage alloy electrode

A probe card provides electrical connection between an IC device under test (DUT) and a testing apparatus. The probe card includes: a test chip for transferring a signal between the DUT and the testing apparatus; and a contact bump provided at a position corresponding to a pad of the test chip, wherein the test chip is provided to securely press the contact bump against the DUT, thereby establishing the electrical connection between the DUT and the contact bump.

Probe card

A method for manufacturing hydrogen storage alloy particles comprises steps of obtaining a melt of the hydrogen storage alloy and pulverizing the hydrogen storage alloy by water atomizing process, whereby the melt is pulverized by contacting or colliding with high-speed jetting thereto to be dispersed in the form of solidified fine particles. By employing an aqueous solution of hypophosphorous acid or an alkali aqueous solution in place of water during the water atomizing process, or by etching the oxide films once formed on the surface of the hydrogen storage alloy particles with an aqueous solution of a strong acid, the thickness of the oxide film can be made thinner, and thus a high discharge capacity of a battery configured with a negative electrode comprising the alloy particles can be realized.

Method for producing hydrogen storage alloy particles and sealed-type

A control system for controlling a cache tag memory has an address conversion device which includes an associative storage for storing logical addresses, a random access memory for storing physical addresses, and a hit-signal generating circuit for generating a hit signal, a word selecting signal and at least one control signal. The hit signal indicates that a hit has occurred between a logical address stored in the associative storage and an input logical address. The address conversion device controls the reading operation of a tag address stored in the cache tag memory by using the control signal generated by the hit-signal generating circuit in synchronization with a word selecting signal used in the reading operation of a physical address stored in the random access memory such that the physical address and the tag address are read at substantially the same time. Further, this address conversion device controls a reading operation of the data stored in the cache memory by reading the physical address and the tag address at substantially the same time and by using a second control signal generated by the hit-signal generating circuit in synchronization with the word selecting signal. Moreover, the address conversion device controls the reading of data from the cache memory and the production of a cache hit signal, which is generated when the physical address matches the logical address. Accordingly, a high-performance system is achieved.

Control systems having an address conversion device for controlling a

The present invention discloses the structure of a MIS capacitor adapted to be interposed between two terminals, i.e., first and second terminals, to be connected to an electric circuit. Formed on a common semiconductor substrate are first and second capacity insulator layers, first and second electrically conductive layers thereon, and first and second impurity diffusion areas under the first and second capacity insulator layers. Also formed are a first wiring line which connects the first electrically conductive layer and the second impurity diffusion area to the first terminal, and a second wiring line which connects the second electrically conductive layer and the first impurity diffusion area to the second terminal. Accordingly, the first electrically conductive layer and the second impurity diffusion area form one electrode, while the second electrically conductive layer and the first impurity diffusion area form the other electrode. With the arrangement above-mentioned, voltage dependencies inherent in capacitors each having a MIS structure are substantially cancelled with each other, resulting in reduction of the voltage dependency of the MIS capacitor. Through a process using one polysilicon layer, there can be formed an economical MIS capacitor having a small area which can be mounted on an analog circuit.

MIS capacitor and a semiconductor device utilizing said MIS capacitor

A hydrogen storage alloy for negative electrodes in an alkaline storage battery is disclosed. The alloy is represented by the general formula MmNi.sub.x M.sub.y, wherein Mm is a misch metal or a mixture of rare earth elements, and M is at least one element selected from the group consisting of Al, Mn, Co, Cu, Fe, Cr, Zr, Ti and V and wherein 5.0.gtoreq.x +y.gtoreq.5.5, and has a microstructure comprising a phase composed of a crystal structure of CaCu.sub.5 type and is capable of absorbing and desorbing hydrogen in a reversible manner, and at least one phase consisting mainly of an element or elements other than Mm, and incapable of storing hydrogen.

Hydrogen storage alloy and nickel-metal hydride storage battery using

As a TLB (translation look-aside buffer) of a fully associative system is organized, a first CAM (content addressable memory) cell array and a first RAM (random access memory) cell array which together make up one entry are arranged in such a way that they face each other across a control circuit. As a cache memory of a fully associative system is organized, a second CAM cell array and a second RAM cell array which together make up one entry are arranged in such a way that they face each other across the control circuit. Additionally, the second CAM cell array is located next to the first RAM cell array, whereas the second RAM cell array is located next to the first CAM cell array. These four cell arrays make up one section. At the time of a hit in the first CAM cell array, the control circuit enables readout of the first RAM cell array, while it, at the time of a hit of the second CAM cell array, enables readout of the second RAM cell array. Based on logical addresses issued to the first CAM cell array, physical addresses are read from the first RAM cell array. Such physical addresses are supplied to the second CAM cell array as tags for the readout of data from the second RAM cell array.

Semiconductor device having combined fully associative memories

A microprocessor has a CPU, an address converter which converts a logical address to a physical address, first and second latches which are controlled by a control signal and store the physical addresses, and a dual port cache memory device. The dual port cache memory device has decoders which operate according to second parts of outputs of the latches, dual port memory arrays which can be independently accessed by outputs of the decoders, a comparator which compares a physical address output from the dual port memory array and a first part of an output of the first latch to determine if they are the same, and a second comparator which compares a physical address output from the dual port memory array and a first part of an output of the second latch to determine if they are the same. The microprocessor is configured to effectively utilize the two ports of the dual port memory array of the dual port cache memory device, significantly improving the operating speed of the overall system by reducing the occurrence of penalties when consecutive instructions operating the cache memory are executed.

Microprocessor with dual-port cache memory for reducing penalty of

A semiconductor memory device has an address translator and a comparator. An entry of the address translator includes an associative memory cell array for storing and comparing a logical address of at least m bits. A first decoder generates a first word signal for the associative memory cell array. A first random access memory cell array stores a physical address of m bits. A controller generates a word signal for the first random access memory cell according to the first word signal and a result of a comparison by the associative memory cell array. A second random access memory cell stores a physical address of m bits. The second random access memory cell is physically disposed near the first random access memory cell array. A second decoder generates a second word signal for the second random access memory cell array. Outputs of the first and second random access memory cell arrays are connected to and compared by the comparator which outputs a signal upon coincidence between the outputs of the first and second random access memory cell arrays.

Memory device having address translator and comparator for comparing

An instruction supplier for a microprocessor prevents a functional error operation of the microprocessor. In the instruction supplier, an instruction register temporarily stores an inputted instruction therein, and an instruction memory stores at least one instruction therein. At least one comparator is provided for detecting whether or not at least one instruction stored in the instruction memory agrees with the instruction stored in the instruction register, respectively, by comparing them, and for outputting a comparison result signal for indicating the comparison result. Furthermore, an instruction generator generates at least one specific instruction in accordance with the comparison signal, and then, an instruction selector selects either one of the instruction stored in the instruction register and the specific instruction generated by the instruction generator to be executed, and outputs the selected instruction.

Instruction supplier for a microprocessor capable of preventing a

A cache memory device including first and second address selectors and a control device for controlling the selection of two addresses out of four types of addresses. The four address types are instructions addresses successively generated by an increment of a program counter, a branch address for instruction fetch in a branch target based on a conditional branch instruction or the like, a data address for data access based on load instruction or store instruction, and a physical address for regulating data consistency between the cache memory device and other memory devices. A first memory array for storing tag addresses and a second memory array for storing instructions and data have two ports to access two selected addresses received from the first and second address selectors independently. Accordingly, access penalties by an RISC microprocessor are reduced in a processor unit in a multiprocessor system.

Cache memory for efficient access with address selectors

The invention discloses a PLL formed by a phase detector, a filter, three VCO's (VCO1, VCO2, and VCO3), a multiplexer, and a frequency divider. The VCO1, VCO2, and VCO3 have different mean frequencies, each oscillating at a frequency controlled according to the voltage value of a phase control signal from the filter. The multiplexer selects one of the VCO's which operate in parallel. If a pulse of a digital phase difference signal UP indicating that an internal signal is delayed in phase with respect to a reference signal is output twice in succession, or if a pulse of a digital phase difference signal DOWN indicating that an internal signal is advanced in phase with respect to a reference signal is output twice in succession, a counter makes the multiplexer change its current VCO selection via a shift register. Accordingly, high-speed PLL pulling is achievable even if a PLL frequency variable-range is expanded.

Phase locked loop having plural selectable voltage controlled oscillators

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Osaka, Japan

Seiji Yamaguchi