Hitachi, Ltd.

Hitachi Computer Eng. Co., Ltd.

Seiji Nagai

Toshiyuki Kinoshita

Shunji Tanaka

Fujio Wakui

Masaichiro Yoshioka

Hiromichi Kainoh

Takaaki Nishiyama

Tadashi Nota

In a fault recovery method for a multi-processor system including a main storage and a plurality of virtual machines which are assigned to a plurality of processors under control of a host operating system and a plurality of guest operating systems and which operate on the processors associated therewith, a fault occurring in one of the processors is detected to recover functions of the system. The method includes the steps of setting recovery attributes for failure to each of the virtual machines, assigning a plurality of virtual machines to a plurality of processors and operating the virtual machines on the processors respectively associated therewith, storing, at detection of occurrence of a fault in one of the processors, data and status information of virtual machines assigned to the processor and status information of the processor respectively in a virtual machine save area and a real machine save area of the main storage, storing fault information of the processor in the main storage by a fault recovery circuit having received a report of the fault, restarting an interrupted process and causing an interruption according to the status information of the virtual machines and the status information and fault information of the processor which are obtained from the main storage, and retrieving, when the interruption is received, one of the virtual machines assigned to the processor according to the processor status information in the real machine save area and then assigning the plural virtual machines to the plural processors for operation thereof according to the recovery attributes for failure set to the retrieved virtual machine.

Fault recovery method and apparatus

A data processing system includes a multistage pipeline arithmetic/logic operation unit for implementing an arithmetic or logic operation for sets of element data sequentially and storing operational results sequentially in a memory using a single instruction. Check information indicative of the presence or absence of a fault occurring in each stage of the pipeline operation unit is moved in synchronism with the advancement of stages of the pipeline operation unit. A request control unit for storing the operational result in the memory suppresses the storing of the operational result in the memory if check information indicates a fault of the operational result which is being stored in the memory. The request control unit issues storage requests, which are counted by a counter. The counter indicates the number of elements stored normally in the memory.

Data processing system having pipeline arithmetic/logic units

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Hadano, Japan

Seiji Nagai