International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

Seiji Munetoh

Ghavam G Shahidi

Nobuyuki Ohba

Hiroshi Maruyama

Frank Robert Libsch

Kohji Hosokawa

Sachiko Yoshihama

Daniel Joseph Friedman

Nobuaki Takahashi

Chitra K Subramanian

Yasunao Katayama

Hideto Niijima

Hiroki Murata

Devendra K Sadana

Chung H Lam

Vijay Narayanan

Toshiaki Kirihata

Dirk Pfeiffer

Ramachandran Muralidhar

Eduard Albert Cartier

Robert L Wisnieff

Richard Harold Boivie

Brian L Ji

Charanjit Singh Jutla

Atsuya Okazaki

Yoshinao Kobayashi

Wanki Kim

Chandrasekara Kothandaraman

Chorng-Lii Hwang

Lawrence Alfred Clevenger

Nicholas Anthony Lanzillo

Nataraj Nagaratnam

Kohichi Kamijoh

Masami Tada

Geoffrey W Burr

Akihiro Horibe

Kuniaki Sueoka

Akira Ohkado

Yasuteru Kohda

Akashi Satoh

Yukihiko Sohda

Tadayuki Okada

Frank Seliger

Biswanath Senapati

Stephen Victor Kosonocky

Shoko Suzuki

Naohiko Uramoto

Arun Paidimarri

Shohei Hido

Abhilash Narendra

Timothy David Ebringer

Nobuyuki Oba

Tim Ebringer

Toshiaki K Kirihata

An IC memory device includes a substrate and an array of memory cells on the substrate. Each memory cell includes at least one memory cell transistor in a layer of the device adjacent to the substrate. In the same layer, the device also includes a plurality of shunt transistors. The device also includes a buried metal signal rail, which is disposed between the array of memory cells and the plurality of shunt transistors in a buried layer that is embedded into the substrate below the transistors. The device also includes single-layer vias, which are in same layer as the transistors and electrically connect the memory cell transistors to the shunt transistors through the buried metal signal rail.

Buried metal signal rail for memory arrays

A memory cell in a backside of a wafer and methods of forming the memory cell are described. A buried metal structure can be formed through a frontside of a substrate. At least one device can be formed on the frontside of a substrate, where the at least one device can be connected to the buried metal structure in the substrate. A through silicon via (TSV) can be formed through a backside of the substrate, where the TSV can be connected to the buried metal structure. A memory cell can be formed on the backside of the substrate, where the memory cell can be connected to the TSV.

Memory cell in wafer backside

A processor-implemented method imposes trust at the edge of a blockchain. A hardware interrogator in a terminal interrogates an Internet of Things Smart Device (IoTSD). The IoTSD is an off-line device that is associated with a physical product. The IoTSD includes a cryptographic processor and one or more state sensors that monitor a state of the physical product. The hardware interrogator detects an event that is described by an encrypted entry in the IoTSD. The terminal transmits, to a blockchain, a transaction that describes the event that is detected by the hardware interrogator, such that the blockchain adds the transaction to a blockchain that is dedicated to the physical product, and the blockchain establishes a state of the physical product.

Smart device to impose trust at the edge of a blockchain

A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.

Encryption engine with an undetectable/tamper-proof private key in late node CMOS technology

Devices, computer-implemented methods, and systems that can facilitate radio frequency identification components are provided. According to an embodiment, a device can comprise a memory that can be coupled to an integrated circuit device that can have a processor and an accelerator component that can execute a cryptographic module. The device can further comprise a radio frequency identification device that can be coupled to the integrated circuit device that can communicate with a radio frequency identification reader device based on the cryptographic module.

Radio frequency identification based integrated computer with hardware accelerator

A monitoring device configured to monitor a network to which plural controllers are connected which includes a decoder configured to extract target data belonging to a target data group from data received from the plural controllers, a first comparator configured to determine whether an immutable part of the target data is known or anomalous, a second comparator configured to determine whether a reception interval of the target data group is normal or anomalous, a third comparator configured to determine whether the number of the target data having been received and included in the target data group is normal or anomalous, and determine whether each reception interval between the target data is normal or anomalous, and a warning counter configured to individually count the number of anomalies determined by the first comparator, the number of anomalies determined by the second comparator, and the number of anomalies determined by the third comparator.

Monitoring device monitoring network

An apparatus for data transfer includes a first node connected to a bus to communicate bidirectionally, and second nodes connected in series to the bus. Each second node lacks an internal clock and has fixed pads including a power, a ground, and signal pads to transfer a data frame, return data pads for a return signal, select pads for a selection signal and clock pads for a clock signal. Each second node is indexed by a hop count in the frame that is incremented each time the frame is transferred in topological order. Each second node is selectable using a mode defined by a combination of the hop count, a mask field and an address field in the frame. The signal pads are used for frame transfer in a selected mode controlled by a combination of the selection, clock and return signals.

Daisy-chained serial bus for multiple small footprint devices

Encryption engine with an undetectable/tamper proof private key in late node CMOS technology

Analysis system, analysis method and program. The system includes: trace means for acquiring a command issued by software executed in an information processing system and a physical address of a memory used by the command as trace data, and recording the trace data to storage means; event detecting means for detecting an event caused to occur by the software and acquiring event information; conversion means for converting the event information to a memory access pattern configured with a plurality of commands for accessing the memory and a plurality of physical addresses; and memory accessing means for accessing the memory using the converted memory access pattern, causing the trace means to acquire trace data and record the trace data to the storage means.

Analysis system, analysis method and program

A system and method of avoiding loss of memory trace data, including monitoring a first-in-first-out (FIFO) buffer to determine if the FIFO buffer has overflowed due to memory access, determining whether an overflow of the FIFO buffer is acceptable, changing an operating mode of a target system if overflow of the FIFO buffer is unacceptable to avoid FIFO buffer overflow, and collecting memory trace data on the memory accesses.

Dynamic bandwidth throttling of DRAM accesses for memory tracing

A semiconductor structure includes a first processor on a first die of a substrate. There is a second processor on a second die of the substrate. There is a one-time programmable (OTP) memory programming circuit, outside of the first and second die, and shared by the first and second processors. Each of the first and second processors include a one-time programmable (OTP) memory. The OTP memory programming circuit is configured to program each OTP memory.

System implementation of one-time programmable memories

A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region.

Wafer scale testing and initialization of small die chips

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Tokyo, Japan

Seiji Munetoh