Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Seiji Miyamoto

Tatsuya Nagata

Hideko Ando

Takeo Yamada

Mitsuo Usami

Kanji Otsuka

Takayuki Okinaga

Shigeo Kuroda

Takashi Iida

Toshihiro Matsunaga

Masao Kato

Kunizo Sahara

Yuuji Shirai

Takashi Kumagai

Hiroshi Tachi

Masayuki Kawashima

Tatsunobu Abe

Kazutoshi Kubo

A semiconductor packaging substrate with a plurality of pads arranged in a square grid pattern thereon, in which among the pads, two pads obliquely adjacent to each other are connected with through-holes respectively and another through-hole is provided between the through-holes connected with the two pads obliquely adjacent to each other.

Semiconductor packaging substrate and semiconductor device

A BGA semiconductor device for high-speed operation and high pin counts has a base which is constituted by a core layer formed of wiring boards and surface layers provided on both sides of the core layer, and a semiconductor element mounted on the base. Through holes in a signal region of the core layer are disposed in an optimum through hole pattern in which power through holes and ground through holes are disposed adjacent to signal through holes.

Semiconductor device

The invention eliminates a need to increase a size of a semiconductor device and reduces occurrence of noise. A semiconductor device of the invention includes: a base () having front layers () provided on respective sides of a core layer () formed by a printed circuit board, and a semiconductor chip () mounted on the base (), wherein the semiconductor chip () is joined to one () of the front layers by using a joining member (), and the other front layer () has a plurality of external terminals () arranged thereon, and the core layer () has a plurality of through-holes () formed therein to electrically connect the semiconductor chip () to the plurality of external terminals () together, and the plurality of through-holes () include a plurality of arrayed through-holes () arranged correspondingly to the arrangement of the plurality of external terminals () and one or more additional through-holes () formed between the plurality of arrayed through-holes ().

Control of the characteristic impedance of wirings is performed with high accuracy. Relative to a first wiring of a second wiring layer arranged above a through hole of a core layer in a package board, the thickness of a first insulating layer between a first wiring layer on the surface of the core layer and the second wiring layer is made large, and the thickness of a second insulating layer between a third wiring layer that is a plane layer on the side of opposite thereto and the second wiring layer is made small, thereby allowing for: reducing the impedance coupling between the power plane of the first wiring layer on the surface of the core layer and the first and second wirings; reinforcing the impedance coupling between the power plane of the third wiring layer on the side opposite thereto and the first and second wirings; and achieving the reduction of the difference in the characteristic impedance between the first wiring arranged just above the through hole and the second wiring arranged away from just above the through hole.

Attempts have been made to increase the number of pins of packages accompanying the trend toward fabricating integrated circuits highly densely and in smaller sizes. The present invention provides technology for improving reliability in fabricating packages of the surface-mounted type that have increased number of pins. That is, when the packages are mounted on the wiring substrate, the lead pins that receive load from the axial direction exhibit bending strength which is smaller than the junction strength of solder at the junction portions. To achieve this object, the lead pins are made of a material having large resiliency such as a fiber-reinforced material, a transformation pseudo elastic material, an ultra-high tension material, or a heat-resistant ultra-high tension material.

Semiconductor device having leads for mounting to a surface of a printed

Growing community of inventors

Tachikawa, Japan

Seiji Miyamoto