Hitachi, Ltd.

Renesas Technology Corp.

Renesas Electronics Corporation

Spansion Llc.

Disco Corporation

Micron Technology Incorporated

Elpida Memory, Inc.

Hitachi-lg Data Storage, Inc.

Ps4 Luxco S.a.r.l.

Hitachi Ulsi Systems Co., Ltd.

Seiji Miura

Kazushige Ayukawa

Yoshikazu Saitou

Hiroyuki Mizuno

Takao Watanabe

Kazumasa Yanagisawa

Yusuke Kanno

Jun Satoh

Kenzo Kurotsuchi

Roger Dwain Isaac

Hiroshi Uchigaito

Kazuhiko Abe

Shoji Kaneko

Satoru Hanzawa

Junichi Miyakoshi

Yoshinori Haraguchi

Tetsuya Iwamura

Hiroki Uryu

Hiroyuki Minemura

Takashi Naito

Hiroki Yamamoto

Yoshinori Matsui

Yoshitaka Sasago

Seiichi Watanabe

Takuya Aoyagi

Takahiko Kato

Sadashi Tanaka

Kunio Takada

Masayuki Yamada

Koichi Shigematsu

Hidenori Akamatsu

Akira Manabe

Shinichi Shimoda

Yoshiki Kobayashi

Hisatoshi Fujisawa

Kouichi Hoshi

Yutaka Shimada

Akira Yabu

Haruhiko Asahi

Norihito Sakaguchi

Kazuki Aoshima

Kenji Ohkubo

A laser beam irradiating unit of a laser processing apparatus includes a laser oscillator, a mirror configured to reflect a laser beam emitted from the laser oscillator and propagate the laser beam to a processing point, a power measuring unit configured to measure power of leakage light of the laser beam transmitted without being reflected by the mirror, and a condensing lens configured to condense the laser beam propagated by the mirror and irradiate a workpiece with the condensed laser beam. The control unit measures the power of the leakage light of the laser beam by the power measuring unit while irradiating the workpiece with the laser beam.

Laser processing apparatus

A laser oscillator support table includes a base, a fixed plate supported over the base with intermediary of a Z-axis direction movement unit, and a Y-axis direction moving plate mounted on the fixed plate, movable orthogonal to an X-axis direction. An optical path direction of the beam emitted from a laser oscillator supported by the laser oscillator support table is defined as the X-axis direction. The laser oscillator support table further includes a rotating plate that is mounted on the Y-axis direction moving plate rotatably around a rotation center pin fixed to the Y-axis direction moving plate and supports the laser oscillator, a Y-axis direction movement unit that moves the Y-axis direction moving plate in the Y-axis direction, and a rotational movement unit that rotates the rotating plate around the rotation center pin in a plane parallel to a plane formed by the X-axis direction and the Y-axis direction.

Laser oscillator support table and adjustment method of laser oscillator support table

An optimization system has a plurality of nodes, each including: a calculation processing unit that calculates an optimum value of a determination variable representing a parameter that controls the nodes by using the ADMM; and a function value calculation unit that receives an input of a value of the determination variable and calculates the value of the objective function based on a calculation model constructed by a learning processing. An arbitrary value of the determination variable is input to the function value calculation unit, and the calculation processing unit substitutes the value of the objective function calculated by the function value calculation unit and the arbitrary value of the determination variable into a second optimization problem by dual transformation of the first optimization problem, thereby repeatedly executing a processing of calculating a value of the dual variable until the value of the dual variable satisfies a predetermined condition.

Optimization system and optimization method

Disclosed is a nonvolatile memory control method in which a unit of erase and a unit of read are different from each other. The control method includes: allocating a physical address of the nonvolatile memory to a logical address in a predetermined unit; and controlling a size of the unit of erase in which a physical address allocated to a logical address is included according to a write access state with respect to the logical address in the predetermined unit.

Nonvolatile memory control method, control device, and semiconductor storage device

A large-scale computer system including a plurality of nodes is controlled to improve its system performance without aggregating data in a single site. There is provided a computer system including a plurality of computers, wherein a processor: detects a trigger to calculate a control value for controlling a process to be performed by the computer; identifies a target computer for which an evaluation value is obtained; calculates the evaluation value of its own computer; obtains the evaluation value from the target computer; calculates a first point using at least one of the evaluation value of its own computer and the evaluation value of the target computer; obtains a second point from the target computer; calculates the control value using the first point and the second point; and controls the process performed by the computer based on the control value.

Computer system and method of controlling computer system

A memory module includes: a first memory device that is volatile or non-volatile; a second memory device that is non-volatile; a third memory device that is non-volatile; and a controller that controls the first to third memory devices, wherein a capacity of the second memory device is larger than a capacity of the first memory device, and a capacity of the third memory device is larger than the capacity of the second memory device, a second upper limit value of the number of rewritings of the second memory device is larger than a third upper limit value of the number of rewritings of the third memory device, and a first upper limit value of the number of rewritings of the first memory device is larger than the second upper limit value of the number of rewritings of the second memory device, and the controller accesses the second memory device with reference to a first address translation table related to the second memory device stored in the first memory device, and accesses the third memory device with reference to a second address translation table related to the third memory device stored in the second memory device.

Memory module and information processing system

An information processing device includes a host and a memory subsystem. The host issues an identifier indicating a data erasable order and a data write command to the memory subsystem and includes an information processing circuit for processing the data. The memory subsystem includes a first memory and a control circuit for writing the data in the first memory. The first memory has a data erase unit size larger than a data write unit size. The control circuit classifies the data based on the identifier, writes the data belonging to a first group in a first simultaneous erase region, in which data can be simultaneously erased, in the first memory, and writes the data belonging to a second group different from the first group in a second simultaneous erase region, in which data can be simultaneously erased, in the first memory. Consequently, the performance and the life of a storage device can be improved, and costs of the storage device can be reduced.

Information processing device

An object of the present invention is to realize a highly reliable long-life information processor capable of high-speed operation and easy to handle. The processor includes a semiconductor device comprising a nonvolatile memory device including a plurality of overwritable memory cells, and a control circuit device for controlling access to the nonvolatile memory device. The control circuit device sets assignments of second addresses to the nonvolatile memory device independently of first addresses externally supplied, such that the physical disposition of part of the memory cells used for writing of first data to be written externally supplied is one of the first to (N+1)th of every (N+1) memory cells (N: a natural number) at least in one direction.

Semiconductor device having a write prohibited region

An object of this invention is to provide a semiconductor memory device capable of increasing the read transfer rate by performing the read operation in parallel while suppressing the voltage drop when a large current is passed to a memory chain and reducing a chip area by reducing the number of peripheral circuits to feed power. A semiconductor memory device according to this invention includes upper and lower electrodes in a flat plate shape, first and second select transistors extending in first and second directions respectively, and a wire arranged between the first select transistor and the second select transistor and the wire and the lower electrode are configured to be electrically insulated from each other by turning off the first select transistor (see FIG.).

Semiconductor storage device

A data archive system includes a data library apparatus and a server. The data library apparatus includes recording media having recording surfaces on both surfaces, a recording media storage unit for storing the recording media, a recording/reproducing unit for the surface for recording/reproducing the data on/from the surface of the recording media, a recording/reproducing unit for the rear surface for recording/reproducing the data on/from the rear surface, and a recording media transporting unit for transporting the recording media between the recording media storage units. The server includes a data configuration unit for allocating the data for recording on the surface and the rear surface of the recording media and a controller for controlling the data library apparatus. The data configuration unit of the server alternately allocates the recording data on the surface and the rear surface of the recording media different from each other.

Data archive system

The non-volatile storage solid state drive (SSD) has non-volatile memory (NVM), random access memory (RAM) capable of being accessed at a higher speed than this NVM, and a control unit for controlling accesses to the NVM and to the RAM. The control unit stores in the NVM an address translation table that translates a logical address given to access this NVM to a physical address after dividing it into multiple tables, and stores in the RAM the multiple address translation tables-sub on RAM that have been divided into multiple tables.

Non-volatile storage addressing using multiple tables

A semiconductor device including a nonvolatile memory cell realizes enhancement of reliability and convenience. The semiconductor device includes a nonvolatile memory unit that includes plural overwritable memory cells (CL), and a control circuit that controls access to the nonvolatile memory unit. The control circuit allocates one physical address to a chain memory array CY in the nonvolatile memory unit, for example. The control circuit performs writing to a memory cell (for example, CL) that is apart of the chain memory array CY according to a first write command with respect to the physical address, and performs writing to a memory cell (for example, CL) that is another part thereof according to a second write command with respect to the physical address.

Semiconductor device

A control circuit of a semiconductor device (memory module) realizes long life and others by a mechanism that suppresses and smoothes variations in use of a memory by equalizing the sizes of data write and data erase with respect to a data write request and sequentially allocating and using addresses of the memory in data write to an overwritable non-volatile memory device without carrying out an overwriting operation even in the case of an overwrite request. The control circuit realizes data write by a set of two types of operations of (a) an operation of erasing data of a first address or an operation of setting a flag value to an invalid state and (b) an operation of writing data to a second address different from the first address or an operation of setting a flag value to a valid state.

Semiconductor device and method of controlling non-volatile memory device

An information processor includes an information processing sub-system having information processing circuits and a memory sub-system performing data communication with the information processing sub-systems, wherein the memory sub-system has a first memory, a second memory, a third memory having reading and writing latencies longer than those of the first memory and the second memory, and a memory controller for controlling data transfer among the first memory, the second memory and the third memory; graph data is stored in the third memory; the memory controller analyzes data blocks serving as part of the graph data, and performs preloading operation repeatedly to transfer the data blocks to be required next for the execution of the processing from the third memory to the first memory or the second memory on the basis of the result of the analysis.

Information processor

A high-speed, low-cost data processing system capable of ensuring expandability of memory capacity and having excellent usability while keeping constant latency is provided. The data processing system is configured to include a data processing device, a volatile memory, and a non-volatile memory. As the data processing device, the volatile memory, and the non-volatile memory are connected in series and the number of connection signals are reduced, the speed is increased while keeping expandability of memory capacity. The data processing device measures latency and performs a latency correcting operation to keep the latency constant. When data in the non-volatile memory is transferred to the volatile memory, error correction is performed to improve reliability. The data processing system formed of these plurality of chips is configured as a data processing system module in which the chips are disposed so as to be multilayered each other and are connected by a ball grid array (BGA) or a technology of wiring these chips.

Semiconductor device and data processing system

Growing community of inventors

Hachioji, Japan

Seiji Miura