Kabushiki Kaisha Toshiba

Seiji Koino

Toshiyuki Yaguchi

Atsushi Kunimatsu

Hiroyuki Takai

Yuriko Kyuma

Mikio Takasugi

Hiroki Fujimura

An instruction code is received by an instruction input section 103 and then decoded by the instruction decode section 105 to generate an operand and control signals. The instruction division control section 109 generates a division control signal based on the control signals and an operand selection section 107 generates an operand having a desired bit width by using the operand from the instruction decode section 105 based on the division control signal. An arithmetic section 111 divides the operand into a desired bit width parts based on the division control signal and performs arithmetic operation. A memory access control section 115 receives calculated address and transfers this calculated address and the division control signal to a memory. The memory access control section 115 receives data from the memory and transfers the data into the arithmetic result store section 113.

Processor architecture with divisional signal in instruction decode for

A microprocessor having a register bank architecture has n register banks, a memory, a bus for connecting the register bank and the memory, and a bank controller for controlling store/load operations between the register banks and the memory. The controller has a current bank pointer indicating data region of the register banks and the memory during the data store/load operations, and a bank size designation register indicating a bank size to be stored/loaded during the store/load operations. When an address of the current bank pointer is set in an destination operand in an instruction, the controller receives the contents of the current bank pointer and bank size designation register. The controller controls the store operation for the n register banks based on the current bank pointer and the bank size designation register, and changes the content of the current bank pointer with the content of the destination operand in the instruction after the completion of the data store operation, receives the content of the current bank pointer and the content of the bank size designation register, and controls the load operation for the memory by the contents of the current bank pointer and bank size designation register.

Microprocessor having register bank architecture

A microprocessor having a register file has an execution unit, a register file for storing data or information for a task, and a bank ram. The register file includes a stack pointer, a general purpose register group having a plurality of registers for storing data used for the execution unit, and a special purpose register group for storing data of a task. The special purpose register group includes a current bank pointer, a processor status word (PSW), a preceding bank pointer, and a program counter. The bank ram is made up of a plurality of bank blocks. Each bank block consists of a predetermined unit banks. Each bank block is capable of storing the data of the register file per task. In the microprocessor described above, when a current task is switched to another task, the content of the stack pointer of the current task is set as one of the registers in the general purpose register group. The number of the unit blocks per bank block and the bit width of the stack pointer can be changed by the PSW.

Growing community of inventors

Tokyo, Japan

Seiji Koino