Osaka University

Nihon Kohden Corporation

National Institute of Information and Communications Technology, Incorporated

Spchange, Llc.

Seiji Kameda

Masayuki Hirata

Katsuyoshi Suzuki

Takafumi Suzuki

Hiroshi Ando

Kaoru Imajo

Takatsugu Kamata

A resistance device () includes a field-effect transistor (TN) and a voltage applying circuit (). The voltage applying circuit () applies a control voltage (Vgs) between the gate and source of the field-effect transistor (TN) according to a temperature (T) to control a resistance value (R) between the drain and source of the field-effect transistor (TN). The control voltage (Vgs) is a voltage obtained by adding a correction voltage (Vc) to a reference voltage (Vgs). The correction voltage (Vc) depends on the temperature (T) and is set to be zero at a first temperature (T).

Resistance device, integrated circuit device, implantable device, and correction factor determining method

An internal device () is implanted in a living body (). A control section () causes a communication section () to wirelessly transmit data corresponding to electroencephalogram signals of the living body () which are detected through a group of N (N is 2 or more) electrodes, to an external device (). When the communication section () receives a designation signal designating a group of M electrode(s) (), M being smaller than N, the communication section () is caused to transmit data corresponding to electroencephalogram signals of the living body () which are detected through the group of M electrode(s) (), to the external device () in real time.

Brain-machine interface system capable of changing amount of communication data from internal device, and control method therefor

An internal device of a brain-machine interface system includes: an electrode group including N electrodes, N being 2 or more; an amplification element group including N amplification elements; a communicator communicating with an external device; and a controller selectively executing one of: a normal operation mode in which electroencephalogram signals acquired through the N electrodes are supplied to the amplification element group in a manner that each of the N electrodes corresponds to a respective one of the N amplification elements, and N amplified electroencephalogram signals are transmitted; and a noise-reduction operation mode in which an electroencephalogram signal acquired through an M electrode of the electrode group is supplied to the amplification element group in a manner that each M electrode corresponds to respective plural ones of the amplification elements, and an M amplified electroencephalogram signal is transmitted, M being smaller than N.

Internal device of brain-machine interface system including noise reduction technique, and method of controlling the internal device

Growing community of inventors

Suita, Japan

Seiji Kameda