Yamaha Corporation

Seiji Hirade

Takahisa Yamaha

Masao Noro

Nobuaki H Tsuji

Terumitsu Maeno

Ryohsuke Ohtani

Masayoshi Omura

Tamito Suzuki

Yukitoshi Suzuki

Yoshiki Kasahara

Yuusaku Ebihara

The present invention provides a condenser microphone, in which, with a simple manufacturing process, vibration characteristics of a diaphragm are improved, and a parasitic capacitance occurring between the diaphragm and a back plate is reduced, thus improving sensitivity. Specifically, the diaphragm having a gear-like shape including a center portion and a plurality of arms and the back plate having a gear-like shape including a center portion and a plurality of arms are positioned opposite to each other above a substrate, wherein the arms of the diaphragm and the arms of the back plate are not positioned opposite to each other. Alternatively, it is possible to independently support the diaphragm and the back plate above the substrate. Furthermore, it is possible to support the back plate above the substrate by means of a plurality of supports inserted into a plurality of holes formed in the center portion of the diaphragm.

Condenser microphone

There is provided a mixing recorder which enables the user to readily produce music using overdubbing and/or other recording techniques while suppressing degradation of sound quality to the minimum and enables the user to easily find out his/her desired mixing result from a large number of mixing results obtained in the process of mixing. An audio signal is input, and a source file is read out from a memory card and an audio signal is reproduced based on the source file. The input audio signal and the reproduced audio signal are mixed into a mixed signal, which is then stored as a new source file in the memory card. The source file stored in advance in the memory card is backed up before the new source file is stored in the memory card, and in the back-up, the source file is automatically backed up by generating a file given a new name associated with a name of a source file to be backed up and having the same contents as the contents of the source file.

Mixing recorder, control method therefore, and computer-readable medium including program for implementing the control method

There is provided a portable mixing recorder which enables a user to readily produce music using overdubbing and/or other recording techniques while suppressing degradation of sound quality to the minimum without excessive concern for space restriction. An input analog audio signal is converted to a digital audio signal by an A/D converter section. A decoder reads out a compressed audio signal from an original source file stored in a memory card, and then extends the compressed audio signal to a digital audio signal. A mixing section mixes the digital audio signal obtained by the A/D conversion by the A/D converter section and the digital audio signal obtained by the extension by the decoder. An encoder compresses the digital audio signal obtained by the mixing by the mixing section to a compressed audio signal (mixed file). The mixed file obtained by the compression by the encoder is stored as a new source file in the memory card.

Portable mixing recorder and method and program for controlling the same

A lateral PNP transistor PB and a lateral NPN transistor NB are serially connected between an input terminal and a reference potential (ground potential). In the transistor PB, a diode Dis formed. In the transistor NB, a diode Dis formed. When an ESD of +2000 V is input, the transistor NB turns on, whereas when an ESD of &#x2212;2000 V is input, the transistor PB turns on. The level of a positive signal capable of being input is limited by the inverse breakdown voltage (e.g., 18 to 50 V) of the diode D, whereas the level of a negative signal capable of being input is limited by the inverse breakdown voltage (e.g., 13 to 15 V) of the diode D.

Semiconductor input protection circuit

A p type well region, a field insulation film, a gate insulation film, and a gate-use poly-Si layer are formed on the surface of a silicon substrate, after which a laminate of a silicon nitride layer and a resist layer is used as a mask in ion implantation, which forms a low-concentration source region, Source contact region, drain region, and drain contact region. Side spacers are formed on both side walls of the gate-use poly-Si layer, after which the laminate of the gate-use poly-Si layer, the side spacers, and the gate insulation film is used along with the field insulation film as a mask to perform ion implantation via the silicon nitride layer, which forms a high-concentration source region and drain region. After a silicide conversion treatment, the unreacted metal is removed, which forms a silicide layer.

Semiconductor device having MOS transistor

A p type well region, a field insulation film, a gate insulation film, and a gate-use poly-Si layer are formed on the surface of a silicon substrate, after which a laminate of a silicon nitride layer and a resist layer is used as a mask in ion implantation, which forms a low-concentration source region, source contact region, drain region, and drain contact region. Side spacers are formed on both side walls of the gate-use poly-Si layer, after which the laminate of the gate-use poly-Si layer, the side spacers, and the gate insulation film is used along with the field insulation film as a mask to perform ion implantation via the silicon nitride layer, which forms a high-concentration source region and drain region. After a silicide conversion treatment, the unreacted metal is removed, which forms a silicide layer.

A method of fabricating a semiconductor device having a multi-layered wiring and including dummy wiring not contributing to connection of circuit elements, comprising the steps of: a) preliminarily preparing relationship between width of an isolated lower level wiring and thickness of an interlayer insulating layer with a planarized function formed on the isolated lower level wiring; b) preparing experimental results by forming dense wiring patterns in a first region on a semiconductor substrate, forming an interlayer insulating layer with a planarized function thereon, and measuring thickness of the interlayer insulating layer; c) determining a width of a dummy wiring to be disposed below an isolated upper level wiring, based on the relationship and the measuremental result; d) forming dense lower level wirings in a first region on another semiconductor substrate and a single lower level wiring having the desired width as a dummy wiring only at a location where an upper level wiring is to be formed in a second region on another semiconductor substrate, where an isolated wiring is to be formed as an upper level wiring; e) forming an interlayer insulating layer with a planarizing function to cover the lower level wirings; and f) forming an upper level wirings on the interlayer insulating layer in the first and second regions. A semiconductor device with a multi-layered wiring can be manufactured using a small quantity of data and has upper level wirings on the surfaces of a substantially same level.

Method of fabricating a semiconductor device having a multi-layered

Semiconductor device and fabrication method thereof

Regions of n.sup.+ - and p.sup.+ -types of a semiconductor device are interconnected with a laminated wiring having a low wiring resistance. On the surface of a semiconductor substrate (10), an insulating film (20) is formed covering a field insulating film (12). Contact holes for the n.sup.+ - and p.sup.+ -type regions are formed in the insulating film (20) at areas corresponding to the n.sup.+ - and p.sup.+ -type regions. Thereafter, a refractory metal layer (30A) such as Ti for forming an ohmic contact having a thickness of 100 angstroms or less, an impurity diffusion preventing conductive layer (32A) such as TiN layer, and a refractory metal layer or refractory metal silicide layer (34A) such as W or WSi layer, are formed sequentially in this order from the bottom. A laminated structure of these layers (30A, 32A, 34A) is patterned to form a wiring layer (36). The laminate is subjected to rapid thermal annealing for ohmically contacting the laminate to the n.sup.+ and p.sup.+ -type regions.

Method of manufacturing a laminated wiring structure preventing impurity

After a MOS transistor having a gate electrode layer is formed on the surface of a semiconductor substrate, a first interlayer insulating film and a moisture blocking film are sequentially formed. After necessary contact holes are formed in the films, a first wiring layer is deposited and patterned together with the underlying blocking film, to form wiring layers for the connection to the transistor regions and a moisture blocking pattern covering the gate electrode layer. The first wiring layer includes a lowest Ti layer, Al alloy layer, and other layers. After a second interlayer insulating film is formed covering the first wiring layers, a second wiring layer is formed on the second interlayer insulating film. The second interlayer insulating film contains a spin-on-glass film which contains moisture. The wiring material layer prevents diffusion of moisture from the second interlayer insulating film to the electrode layer, and the moisture blocking film prevents the absorption and store of moisture related species (H.sub.2 O, OH.sup.-, H.sup.+) by the Ti layer of the wiring material layer.

MOS transistor with good hot carrier resistance and low interface state

A field insulating film and a gate insulating film are formed on the surface of a semiconductor substrate, and thereafter contact holes for a source and drain are formed in the gate insulating film. Polycrystalline Si containing impurities are deposited on the substrate and patterned to form source, gate, and drain electrode layers. The source and drain regions are formed by implanting impurity ions and doping the impurities in the source and drain electrode layers to the substrate surface. An interlayer insulating film having a flat surface is thereafter formed on the substrate, and contact holes are formed in the interlayer insulating film by selective etching. The etching depths of the contact holes are generally the same, preventing an excessive etching of the contact hole for the gate electrode.

Growing community of inventors

Hamamatsu, Japan

Seiji Hirade