Elpida Memory, Inc.

Hitachi Automotive Systems, Ltd.

Hitachi, Ltd.

Other

Hitachi Tohbu Semiconductor, Ltd.

Renesas Eastern Japan Semiconductor, Inc.

Seiji Funaba

Yoji Nishio

Yasuo Noto

Masashige Tsuji

Yoshinobu Nakagome

Hideki Osaka

Kayoko Shibata

Yutaka Uematsu

Hiroaki Ikeda

Koichi Yahata

Masashi Horiguchi

Toshio Sugano

Yuichi Okuda

Satoshi Isa

Takuo Iizuka

Masayuki Sorimachi

Kazuyoshi Shoji

Hiroshi Ikeda

Mitsuaki Katagiri

Satoshi Nakamura

Takashi Suga

Tsutomu Hara

Tokihito Suwa

Tomohiko Sato

Susumu Hatano

Yukitoshi Hirose

Yoji Idei

Takao Ono

Koji Hosokawa

Yoshio Akaishi

Hisashi Abo

Keiji Kunii

Tetsuro Tateyama

Koichiro Aoki

Hiroki Shimano

Shinichiro Hida

Yurika Aoki

At the time of clamping, excessive stress is applied to bonding parts between substrates and input/output terminals, which may cause the bonding parts to be detached and cause the substrates to be cracked. A lower electrode of a power semiconductor elementis connected via a bonding materialto a first interconnection layerarranged on a lower surface of the power semiconductor element, and an upper electrodeof the power semiconductor elementis connected via the bonding materialto a second interconnection layerarranged on an upper surface. Also, a second main terminalelectrically connected to the upper electrodeof the power semiconductor elementis connected via the bonding materialto the second interconnection layerand contacts and is positioned on a third interconnection layer(spacer) arranged to be parallel to the first interconnection layeron the lower surface. An insulating layeris laminated on a surface of each of the first interconnection layerto the third interconnection layeropposite the bonding material, and a heat dissipating layeris laminated on the insulating layer

Power semiconductor device including a spacer

In an automotive vehicle inverter control apparatus of the related art, a limp-home mode is provided, but six power sources including transformers are required for respective gate circuits of the respective IGBT drive circuits. Therefore, a reduction in size and a reduction in weight cannot be achieved, and a demand of the improvement of mountability or the improvement of fuel consumption as described above cannot be satisfied. A power semiconductor module and the drive circuit include three unit semiconductor modules and three unit drive circuits corresponding to a three-phase alternating current, and power supply units of the unit drive circuits are provided independently, whereby the limp-home mode is provided and in addition, the number of power supply units may be reduced, so that the reduction in size and the reduction in weight are achieved.

Automotive vehicle inverter control apparatus

A power converter includes an inverter, a contactor for connecting a battery to the inverter in order to supply DC power from the battery to the inverter and for disconnecting the battery from the inverter in order to stop an operation to supply the DC power from the battery to the inverter, a smoothing capacitor connected in parallel to the battery through the contactor, a discharge circuit that is provided with a discharge resistor and a switching device connected in series to the discharge resistor and is connected in parallel to the smoothing capacitor to discharge electric charge from the smoothing capacitor, a voltage measurement circuit, a voltage-dividing circuit for dividing the voltage across the terminals of the smoothing capacitor to generate a partial voltage to be input to the voltage measurement circuit and a control circuit of the switching device.

Power converter

An inverter device includes an inverter circuit, a control circuit, a first drive circuit, a second drive circuit, first and second photocouplers, and a signal switching part. The signal switching part directly transmits the first and second signals outputted from the first photocoupler and the second photocoupler to the corresponding first and second drive circuits respectively when at least one of the first and second signals is an OFF command.

Inverter device

An electric power converter is provided with a plurality of power-conversion elements; a first control circuit that outputs a first control signal; an electricity storage circuit; a second control circuit that outputs a second control signal when the direct-current power source that supplies electrical power to the first control circuit is not normal; and a drive circuit that outputs drive signals for driving the plurality of power-conversion elements. Each of the power-conversion elements is either a power-conversion element of the upper arm connected to the high-voltage side or a conversion element of the lower arm connected to the low-voltage side. In cases when the voltage of the electricity storage circuit is at a higher predetermined first voltage value, the second control circuit outputs a second control signal so that all the power-conversion elements of the upper arm or the lower arm are turned on and the others are turned off.

Power inverter

A power conversion system according to the present invention includes: an inverter circuit unit that converts a direct current power supplied from a direct current source into an alternating current power, the direct current power being supplied to the inverter circuit through a contactor that conducts and interrupts the direct current; a capacitor that smoothes the direct current power; a discharge circuit unit that is connected to the capacitor in parallel, and that includes a discharge resistor for discharging a charge stored in the capacitor and a switching element for the discharge resistor, being connected in series to the discharge resistor; a voltage detection circuit unit that detects voltage between both terminals of the capacitor; a first discharge control circuit that includes a first microcomputer, and that outputs a control signal to control switching of the switching element for discharging; and a second discharge control circuit that outputs an interruption signal to interrupt the switching element for the discharge resistor.

Electric power conversion system

A discharge circuit for a DC power supply smoothing capacitor that is used in a power conversion device that supplies DC power via a switch to the DC power supply smoothing capacitor and an inverter, includes; a resistor that discharges charge in the capacitor; a switch connected in series with the resistor, that either passes or intercepts discharge current flowing from the capacitor to the resistor; a measurement circuit that measures a terminal voltage of the capacitor; and a control circuit that controls continuity and discontinuity of the switch; wherein the control circuit, after having made the switch continuous and starting discharge of the capacitor by the resistor, if a terminal voltage of the capacitor as measured by the measurement circuit exceeds a voltage decrease characteristic set in advance, makes the switch discontinuous and stops discharge by the resistor.

Discharge circuit for smoothing capacitor of DC power supply

A power conversion device includes an inverter circuit converting DC power into AC power and including switching devices constituting upper and lower arms, a control circuit controlling the switching devices, a drive circuit driving the switching devices by a signal from the control circuit, and an insulated power supply circuit supplying power to the drive circuit. The control circuit controls a power supply voltage to be outputted from the power supply circuit to the drive circuit. The drive circuit drives the switching devices and based on a carrier frequency and the power supply voltage. The power supply circuit includes a feedback output circuit through which the voltage outputted to the drive circuit is outputted to a power supply control IC. The feedback output circuit includes a dummy load circuit which controls the voltage to be outputted to the power supply control IC based on a change of the carrier frequency.

Power supply circuit and power conversion device

A COC DRAM including a plurality of stacked DRAM chips is mounted on a motherboard by using an interposer. The interposer includes a Si unit and a PCB. The Si unit includes a Si substrate and an insulating-layer unit in which wiring is installed. The PCB includes a reference plane for the wiring in the Si unit. The wiring topology between a chip set and the COC DRAM is the same for every signal. Accordingly, a memory system enabling a high-speed operation, low power consumption, and large capacity is provided.

Semiconductor integrated circuit device

A semiconductor memory device of the present invention determines a logic level of a signal based on a predetermined reference voltage. And the memory device has an input terminal to which a reference signal having the reference voltage is input, a low-pass filter connected to the input terminal for passing a component of the reference voltage of the reference signal and eliminating undesired high frequency components, and one or more input first-stage circuits to each of which an output of the low-pass filter and a signal having the logic level to be determined are connected. In the memory device, the low-pass filter has predetermined attenuation at least at a frequency of an operating clock.

Semiconductor memory device having input first-stage circuit

An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.

Semiconductor device, memory device and memory module having digital interface

Stacked semiconductor device includes plural memory chips, stacked together, in which waveform distortion at high speed transmission is removed. Stacked semiconductor deviceincludes plural memory chipsstacked together. Data strobe signal (DQS) and inverted data strobe signal (/DQS), as control signals for inputting/outputting data twice per cycle, are used as two single-ended data strobe signals. Data strobe signal and inverted data strobe signal mate with each other. Data strobe signal line for the data strobe signal Lis connected to data strobe signal (DQS) pad of first memory chip. Inverted data strobe signal line for /DQS signal Lis connected to inverted data strobe signal (/DQS) pad of second memory chip

Stacked semiconductor device

A semiconductor module includes a first semiconductor device, a second semiconductor device and a reference voltage supplying circuit. The first semiconductor device includes a first electrode. The second semiconductor device includes a second electrode. The reference voltage supplying circuit is for supplying a reference potential to the first electrode and the second electrode and for suppressing a noise to be transferred between the first electrode and the second electrode.

Semiconductor module

A dummy wiringis provided for simulating an actual wiringconnecting semiconductor integrated circuitsandon a circuit board. The semiconductor integrated circuit comprises a data output circuitcapable of variably setting the slew rate and a circuitfor measuring signal delay time between a signal sending point and a signal reflection point (characteristic impedance mismatching point) using the dummy wiring, and the delay time so obtained by the measuring circuit is used for the determination of the signal transition time of the output circuit. The transition time of the signal is set at least twice of the signal delay time between the signal sending point and the wiring branch at the nearest end. In this way, signal transmission with alleviated reflection by the reflection point at the nearest end is realized.

Semiconductor integrated circuit and electronic device

Growing community of inventors

Tokyo, Japan

Seiji Funaba