Tokyo Shibaura Electric Co., Ltd.

Tokyo Shibaura Denki Kabushiki Kaisha

Seiji Eguchi

Seigo Suzuki

Yoshiaki Moriya

Yutaka Murao

Keiji Namimoto

A memory access control system selects a program mode to carry out a cycle steal operation in response to a logic '1' condition of a predetermined bit position included in a command and selects a direct memory access mode to effect a direct memory access in response to a logic '0' condition of the predetermined bit position.

Memory access control system

An information transferring apparatus comprises a central processing unit, and an input/output unit, a first-in first-out stack having a plurality of memory elements connected in series and being disposed between the central processing unit and the input/output unit, a command register which is set to a predetermined state under program control by the central processing unit, and a control circuit which receives a signal produced from the command register when the command register is set to a predetermined state and applies a signal designating the memory element which is to be the first memory element of the first-in first-out stack from which information is to be transferred and permits the information stored in the first memory element to be read out directly to the input/output unit.

Information transferring apparatus

A multi-processor system includes a plurality of processors, a common shared memory, and programmable memory access priority control circuit. The programmable memory access priority control circuits includes a programmable register circuit and a priority control circuit. The programmable register circuit stores priority information designating a memory access grade priority for each of the processors, wherein the priority information is changeable either manually, by external circuit or by at least one of the processors and remains fixed irrespective of access of the memory by any of the processors until being changed. The register circuit outputs priority information signals which indicate the memory access grade priority of each of the processors. The priority control circuit receives the priority information signals from the register means, receives a memory request signal from the processors requesting memory access (i.e. use) of the common shared memory, and outputs an acknowledge signal enabling the processor having the highest memory access grade priority to use the common shared memory in accordance with the priority information.

Multi-processor system with programmable memory-access priority control

A multi-processor system having a priority control wherein jobs are transferred between processors in a multi-processor system when a new job is accepted by the system. The processors are arranged in a predetermined priority sequence and in response to an interrupt command, the system always directs a transferred job to which priority processor whose currently executing job is transferred to a lower priority processor. Jobs are transferred by shifting linkage information from one processor to the other through a common control memory in accordance with a job transfer program at each processor. When the interrupt cycle is completed, transferred jobs are returned to the processor at which they were being processed prior to the interrupt.

Multi-processor system employing job-swapping between different priority

The data-processing apparatus of this invention comprises a central processing unit (hereinafter referred to as the 'CPU'), and a plurality of a groups of memory units in the CPU to be applied as a general register set. The groups of memory units are provided in a number which is equal to the number of interrupt programs and each group has been previously supplied with information on the individual interrupt programs (such information includes, for example, data on entry address, program status word, etc.). The present data-processing apparatus further has a general register-set pointer provided in the CPU. Where the general register set pointer is supplied with a particular numerical value, the corresponding one of the memory unit groups is selectively used as a general register set.

Data-processing apparatus having improved interrupt handling processor

An operand fetch control system wherein an address modification mode code is provided in the instruction word and designates both the general storage location of an operand to be fetched and the mode of addressing required for fetching it. The address modification mode code is a two-bit binary number designating either a direct register addressing mode or a main memory indirect, index, or indirect index addressing mode. Mode code 00 designates the register mode while the codes 10, 01 and 11 designate the indirect mode, the index mode and the indirect index mode, respectively.

Apparatus and method for operand fetch control

A multi-processor system wherein a plurality of priority-designated central processor units (CPUs) are interconnected by a program control memory which operates to transfer control (linkage) information between CPUs in response to interrupt commands to enable the total processing capacity of the system to be allocated to the highest priority jobs. Each processor unit employs a job swapping control program which responds to an interrupt command from an external source or from a higher priority unit to cause program status data stored in the CPU to be transferred to the program control memory for holding or for passage to a lower priority CPU. The job swapping program also causes program status data from the higher priority CPU to be transferred from the control memory to the CPU to enable processing of a new job. On completion of the interrupt cycle, the control program effects exchange of status data to restore job assignments to the original CPUs.

The system is constructed to operate to mutually transfer information between a processor and a terminal device via a first-in/first-out type stack. Signal generators are provided on the input and output sides of the stack for generating signals corresponding to the EMPTY and FULL statuses of the stack thereby controlling to inhibit or commence the transfer of the information in response to the direction of transfer of the information and the status of the stack.

Information transfer control system

An interrupt control method for a multiprocessor system including a plurality of microprocessors wherein sections of a main memory, which is shared among the processors of the system, are allocated to store entry address data pointing to a plurality of interrupt-servicing programs for each of the several processors of the system. Interrupt commands are coded to designate different interrupt levels which are compared against mask flag bits and a master mask flag bit unique to each processor to determine which processor will respond to the interrupt command. The processors are arranged in a fixed priority sequence and respond to an interrupt command in a designated priority order. Controls are provided to prevent a processor which is executing an interrupt-servicing program from responding to a subsequent interrupt command until execution of the interrupt-servicing program is completed.

Interruption control method for multiprocessor system

The data-processing apparatus of this invention comprises a central processing unit (hereinafter referred to as the 'CPU'), and a plurality of groups of memory units in the CPU to be applied as a general register set. The groups of memory units are provided in a number which is equal to the number of interrupt programs and each group has been previously supplied with information on the individual interrupt programs (such information includes, for example, data on entry address, program status word, etc.). The present data-processing apparatus further has a general register-set pointer provided in the CPU. Where the general register set pointer is supplied with a particular numerical value, the corresponding one of the memory unit groups is selectively used as a general register set.

Data-processing apparatus and method

A processor device which comprises a processor unit integrated in a single chip and integrally assembled with a programming system, thereby providing a direct memory access-controlling function for carrying out a direct memory access between a main memory and an input-output device, and a cycle steal-controlling function for selecting a program mode or direct memory access mode.

Processor device

An entry requirement control system in a multiprocessing system having a plurality of central processing units (CPU's), a common main memory for storing a plurality of programs which are accessed by the CPU's, and a key register provided between the CPU's and the common main memory. A flag bit circuit is incorporated into the system in the form of hardware in the key register and is adapted, upon completion of the execution of a program by one CPU, to only give priority to the earliest entry requirement made by a plurality of CPU's to the same program and prohibit the other CPU's from being given any priority. A flag bit circuit corresponding to each program acts, while one program is executed by one CPU, to prohibit an entry requirement from the other CPU's.

Interruption control system in a multiprocessing system

A data transfer control system for controlling the priority use of a common bus shared by a plurality of data processors which comprises a bus rank memory for storing signals denoting a demand for the priority use of the common bus which are supplied from said plural data processors; and a priority-detecting circuit for detecting the sequential priority positions of signals demanding the priority use of the common bus which are stored in said bus rank memory, wherein the plural data processors are supplied with a control signal instructing the use of the common bus or a waiting position for said use according to the sequential priority positions of the common bus use-demanding signals which have been detected by said priority-detecting circuit.

Data transfer control system

The system comprises a central information processing unit, an input/output unit, a first-in first-out stack which is connected to receive information from the central information processing unit for sending a 'FULL' signal to the central information processing unit when the stack is filled with the information sent from the central information processing unit and for sending thereto an 'EMPTY' signal when the stack is empty, an input/output control circuit which operates to transfer the information from the first-in first-out stack to the input/output unit and to detect the state thereof for sending a 'READY' signal to the central processing unit when the input/output unit is in a state ready for accepting the information, a command register coupled to the central information processing unit to be set at a particular bit by a bit signal sent from the central processing unit when it receives the 'FULL' signal from the first-in first-out stack and the 'READY' signal from the input/output control circuit, and a buffer control circuit energized by the output signal from the command register set at the particular bit for applying a transfer commencement command signal to the first-in first-out stack thereby causing it to transfer information to the input/output unit via the input/output control unit.

An information transferring apparatus disposed between first and second information processing units comprises a first-in first-out stack, a first information line for transferring information from the first information processing unit to the first-in first-out stack, a second information line for transferring information from the first-in first-out stack to the second information processing unit, a third information line for transferring information from the second information processing unit to the first-in first-out stack, a fourth information line for transferring information from the first-in first-out stack to the first information processing unit, switching circuits for selectively deactivating the first to fourth information lines, and a command register for applying first and second control signals to the switching circuits, wherein the switching circuits operate responsive to the first control signal from the command register to deactivate the third and fourth information lines while holding active the first and second information lines, and operate responsive to the second control signal from the command register to deactivate the first and second information lines while holding active the third and fourth information lines. The command register may be replaced and its functions performed by either manual control or an external circuit.

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Kawasaki, Japan

Seiji Eguchi