Mitsubishi Denki Kabushiki Kaisha

Seiichirou Mori

Youichi Tobita

Hiroyuki Murai

Ko Nishino

A level shifter and a charge pump circuit are added, among cascade-connected unit frequency dividing circuits forming a frequency dividing circuit, to the unit frequency dividing circuit in the first stage. The charge pump circuit boosts an input voltage based on a dot clock signal, and supplies the booster voltage to the unit frequency dividing circuit in the first stage. The unit frequency dividing circuit in the first stage, which is driven by the booster voltage, attains an improved current driving capability. The improved current driving capability of the unit frequency dividing circuit in the first stage to which the dot clock signal of high frequency is input leads to a widened operating margin of the frequency dividing circuit.

Frequency dividing circuit, power supply circuit and display device

When a voltage is supplied from a voltage supply terminal to a non-inverted input terminal of an operational amplifier, a voltage equal to the supply voltage is input to an inverted input terminal and also to a voltage apply terminal for a load. When PNP transistors constituting a current mirror turn on in response to the applied voltage, a source current flows through one of the PNP transistors to the load, and a mirror current of the source current flows through the other of the PNP transistors to a current measuring terminal. The current driven to the load can be obtained by measuring the mirror current with an amperemeter.

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Tokyo, Japan

Seiichirou Mori