Oki Electric Industry Co., Ltd.

Oki Semiconductor Co., Ltd.

Seiichiro Sasaki

Kouji Morita

In a pipelined analog-to-digital (AD) converter, if logically incongruent signals Sand Sare output from an AD converter section of a converter stage of the AD converter, a digital-to-analog converter (DAC) section is to be prevented from erroneously operating. When a logically incongruent combination of signals Sand S, such as S='H' and S='L', is output from comparators that compare an input voltage VI to reference voltages +REF/4 and &#x2212;REF/4, an encoder outputs a signal corresponding to a normal signal combination (S=&#x201c;L&#x201d; and S=&#x201c;H&#x201d;) to generate signals X, Y and Z that control switches of the DAC section. This eliminates the risk that the switches shall be turned on simultaneously, thus preventing the erroneous operation of the DAC section.

Encoder for a pipelined analog-to-digital converter

A resistance dividing circuit including silicide layers respectively formed only on branch portions of a linear polysilicon resistance wiring having the branch portions. Contact plugs are connected to the resistance wiring via the silicide layers, and fetching electrodes are respectively connected to the contact plugs.

Resistance dividing circuit and manufacturing method thereof

A current-cell type D/A converter using a timing generating circuit for converting a digital code to the corresponding differential voltage Vout between a first analog voltage and a second voltage includes a plural of current cells and a plural of switch-control-signal generating circuits generating each of switch-control signals being provided each of the above current cells. Each of the above current cells includes the switching NMOSs, and the constant-current sources of the NMOSs.

Timing generating circuit and digital to analog converter using the same

The present invention provides a multilayered power supply line suitable for use in a semiconductor integrated circuit and a layout method thereof. In the multilayered power supply line () for the semiconductor integrated circuit, a top metal () and a second metal () are electrically connected to each other by through holes (). Further, a capacitor metal () is electrically connected to the top metal () by through holes () to thereby make the top metal (), the second metal () and the capacitor metal () identical in potential to one another, whereby the multilayered power supply line functions as a power supply line based on normal wiring metals without functioning as a capacitor. It is thus possible to supply power with reduced impedance.

Multilayered power supply line for semiconductor integrated circuit and layout method thereof

According to the present invention, a multi-layered capacitor includes a first capacitive element having a first conductor plate formed on a first layer, a second conductor plate formed on a second layer and an insulator arranged between the first and second conductor plates; and a second capacitive element which is arranged just on a layer above or below the first capacitive element.

Multi-layered capacitor

An analog-to-digital (AD) converter includes a reference voltage generator for dividing a voltage between a first and a second reference potential to thereby generate low reference voltages of a low level, high reference voltages of a high level side, and medium reference voltages of a medium level. A first voltage comparator compares lower one of the medium reference voltages and an analog voltage input to the AD converter and outputs a first control signal if the analog voltage is higher than the lower medium reference voltage. A second voltage comparator compares higher one of the medium reference voltages and the analog voltage and outputs a second control signal if the analog voltage is lower than the higher medium reference voltage. In response to the second control signal, third voltage comparators each compare particular one of the low reference voltages and the analog voltage. Fourth voltage comparators each compare particular one of the medium voltages and the analog voltage. In response to the first control signal, fifth voltage comparators compare particular one of the high reference voltages and the analog voltage. A data output circuit generates and outputs digital data corresponding to the analog voltage on the basis of results of comparison output from the third, fourth and fifth voltage comparators.

Analog-to-digital converter with a power saving capability

A constant-current power supply circuit includes a bias circuit (20); first and second transistors (11 and 12); an output terminal (OUT); a bias voltage defining circuit (30 & 40); and a compensator (50 or 60). The bias circuit (20) generates a first bias voltage (Vb1). The first transistor (11) supplies a first current (I.sub.1) in response to the first bias voltage (Vb1), supplied from the bias circuit (20). The first current is outputted from an output terminal (OUT). The second transistor (12) is connected between the first transistor (11) and the output terminal (OUT) and is operated in response to a second bias voltage (Vb2). The bias voltage defining circuit (30 & 40) defines the second bias voltage (Vb2). The compensator (50 or 60) is connected to the bias defining circuit (30 & 40) to perform temperature compensation.

Growing community of inventors

Tokyo, Japan

Seiichiro Sasaki