Sony Corporation

Seiichiro Iwase

Masuyoshi Kurokawa

Takao Yamazaki

Mitsuharu Ohki

Kenichiro Nakamura

Mamoru Kanou

Yoshihito Kondo

Hiroshi Okuda

Takashi Asaida

Fumio Nagumo

Norihisa Shirota

Shinichi Komori

Jonathan Coulombe

The characteristic of nonlinear processing with respect to image data is designated by a GUI and the result of the processing quickly displayed. A personal computer displays a GUI image for input on a monitor. When a user designates a nonlinear characteristic on the GUI image by an input device the personal computer extracts a break point approximation function indicating the nonlinear characteristic and displays the same in the GUI image. Further, the personal computer generates a program for executing nonlinear processing indicated by the extracted break point approximation function by a linear array type multiple parallel processor (DSP ) and downloads the generated program to the DSP

Image processor, data processor, and their methods

According to the SIMD control parallel processing method for performing common operation in parallel in a plurality of elements, comprising first retaining means for retaining operation data specified by n-bit for each of said plurality of elements; second retaining means for previously retaining operated result with all possible combinations comprising said data according to a predetermined operation; and selecting means for selecting said operated data retained in said first retaining means from among said operated results retained by said second retaining means, from among retained data obtained through operation, data corresponding to that resultant from the operation is selected for each element, thereby enabling a configuration to be simplified, smaller and less costly.

SIMD control parallel processor with simplified configuration

The present invention relates to an image processing device for converting the number of pixels or scanning lines. In particular, the image processing device according to the present invention comprises an operator for carrying out interpolation operations and a memory for storing filter coefficient sets utilized in the interpolation operations. The memory stores filter coefficient sets each corresponding to each of the phases when the pixel interval of the original image is divided by a prescribed dividing number. Out of these filter coefficient sets, a filter coefficient set that corresponds to the phase closest to that of the pixel data to undergo interpolation operations is then outputted to the operator. The operator then carries out interpolation operations on the pixel data using these filter coefficient sets so that arbitrary format conversion becomes possible.

Image processing device

A picture signal processing device for performing picture signal processing such as conversion of the number of pixels or conversion processing for the number of scanning lines. The picture signal processing device includes a plurality of element processors and a controller for performing common control of said element processors. The element processors arrayed in association with pixels arrayed in one-dimensional direction of a digitized two-dimensional picture. The pixels arrayed in one-dimensional direction are chronologically sequentially entered to the element processors. Each element processor includes a transient memory for transiently storing pixel data, an input pixel data memory for storing input pixel data for transfer to the transient memory, a pixel attribute information memory for storing the pixel attribute information representing the attribute of pixels, a pixel skip information memory for storing the pixel skip information for skipping pixel data, an arithmetic-logic device for carrying out pre-set calculations using the input pixel data or pixel data of near-by element processors based on the pixel attribute information, and an output pixel data memory for storing and outputting the pixel data taken out from the transient memory. The picture signal processing device can cope with conversion processing at an optional ratio.

Picture signal processing apparatus

A digital video signal processor using parallel processing includes an input serial-access memory having memory cells in which data is inputted into successive ones of the memory cells in response to a programmed-controlled pointer and a three or more port data memory unit for writing-in data read out from the serial-access memory. An arithmetic logic unit responds to stored-program control to read out data from the data memory, perform a program-prescribed arithmetic operation, and write the result of the arithmetic operation back to the data memory. An output serial-access memory is controlled so that the arithmetic result will be outputted under program control in a sequential manner. Operation of the interconnected components is effected by a stored-program control unit connected to the input serial-access memory, the data memory, the arithmetic logic unit, and the output serial-access memory.

Video signal processor with triple port memory

A multiple parallel digital signal processor having a large number of bit processing processor elements arranged in one-dimensional array is treated as a processor block, and a plurality of the processor blocks are connected in sequence, while removing redundancy, to form a processor block column. A plurality of processor blocks are connected in sequence such that a processor block at a subsequent stage is supplied either with output of a processor block at a previous stage or with input data, and any of outputs of the processor block columns is delivered as a final output, thereby making it possible to realize a signal processing apparatus which has high performance, versatility, and simple configuration.

Signal processing apparatus

A multiple parallel digital signal processor having a large number of bit processing processor elements arranged in one-dimensional array is treated as a processor block, and a plurality of the processor blocks are connected in sequence, while removing redundancy, to form a processor block column. A plurality of processor blocks are connected in sequence such that a processor block at a subsequent stage is supplied either with output of a processor block at a previous stage or with input data, and an output of any of the processor blocks is delivered as a final output, thereby making it possible to realize a signal processing apparatus which has high performance, versatility, and simple configuration.

A digital signal processing apparatus and information processing system provide sufficient arithmetic operation performance to process high rate signals in real time and high programming performance to deal with various applications. A group of processor elements is constituted by individual processor elements each formed by disposing an arithmetic and logic unit on the bit lines of a multiport memory wherein their number is equal to or larger than the number of the data bits in a series of serial data, and the plurality of processor elements constituting the group of processor elements are uniformly controlled by controllers mounted on the same silicon chip. Consequently, the multiport memory functioning as a buffer for input data and the arithmetic and logic unit are closely joined together, so data can be communicated smoothly between them. Since the plurality of processor elements are controlled by a single controller so as to operate as a parallel computer, a digital signal processor with a high processing speed can be implemented.

Digital signal processing apparatus and information processing system

In a memory device, data stored in memory cells bridging memory cell columns for two lines can be read out in response to an address signal supplied only once. The memory cells (R00-R03), (R10-R13), (R10-R13), (R20-R23)m (R20-R23) and (R30-R33) for the two adjoining lines are connected to common word lines L0, L1, L2. Also, a series of bit lines are sequentially selected by a counter. The data stored in the memory cells bridging the memory cell columns for the two lines can be read out only once by supplying an address signal only one time.

Memory apparatus

A multiport memory having a plurality of serial output ports includes a semiconductor memory for storing data in a plurality of memory elements arrayed in rows and columns and coupled by respective row and column connecting lines. A first register stores data read in parallel from the semiconductor memory via the connecting lines of one of the rows and columns of the arrayed memory elements and serves to supply the data stored therein in serial form to a first one of the serial output ports. The first register is also operative to supply the data stored therein in parallel to a second register for storage therein. The second register is operative to supply the data stored therein to a second one of the serial output ports.

Multiport memory and method of operation thereof

A circuit has a multiple port memory and a plurality of processor elements having write and/or read addresses connected to addresses of the multiple port memory. A register, a delay circuit and/or a buffer memory may be formed among the processor elements in dependence on the connections of the write and read addresses.

Image signal processing circuit having a multiple port memory

A motion vector detection apparatus comprises; delay circuit for receiving first picture data and for outputting a particular detection range of picture data, block comparison circuit for receiving second picture data with a particular time difference from the first picture data and picture data from the delay circuit and for detecting a difference therebetween for each block of (P.times.Q) picture elements, and determination circuit for determining the matching degree of a picture from the output signal produced by the block comparison circuit, wherein the delay circuit comprises scanning conversion circuit for converting input picture data from conventional horizontal scanning into intra-block scanning and a plurality of shift registers for receiving the first picture data with a delay of one frame, wherein the plurality of shift registers are characterized in that both a first block structuring (P.times.Q) picture elements which are earlier than a particular reference tap of the plurality of shift registers and a second block which deviates by i picture elements horizontally and by j picture elements vertically from the first block are set so that when the first block does not deviate from the second block, a tap with a delay which is equal to the difference between each picture element of the second block and the reference tap is selected, the second picture data being obtained from the selected tap.

Motion vector detection and band compression apparatus

An original picture of an interlace system is magnified or reduced by an integer ration of M to N to form a conversion picture. A unit length U is obtained by dividing the distance between vertically adjacent picture elements of the original or the conversion pictures by N or M, respectively. The positions of the picture elements of both fields of the conversion picture are shifted by .vertline.M-N)/4.vertline..multidot.U from the respective positions that would have been occupied by the picture elements of the conversion picture.

Picture element number converter

A digital filter has an input terminal provided with an input digital signal. A delay circuit connected to the input terminal produces a plurality of delayed digital signals each having a different delay time with respect to the input digital signal. A first circuit adds the input digital signal and/or the plurality of delayed digital signals to one or more digital coefficient signals of the same value so as to produce one or more added digital signals. A circuit multiplies the one or more respective digital coefficient signals by the one or more added digital signals and/or one or more of the plurality of delayed digital signals to produce a plurality of multiplied digital signals. A second circuit adds the plurality of multiplied digital signals to produce an output digital signal, and a circuit connected between the delay circuit and a multiplying circuit increases the one or more added digital signals and/or the one or more of the plurality of delayed digital signals by one or more predetermined numbers of times, whereby the one or more respective digital coefficient signals have inversely proportional values corresponding to the one or more predetermined numbers of times of the values of the one or more added digital signals and/or the one or more of the plurality of delayed digital signals.

Digital filter

A digital multiplying circuit in a parallel multiplying circuit which can multiply an input which changes at a high data rate by the pipeline processing. A multiplicand is inputted to this circuit. Partial product signal generating circuits of the number corresponding to only the number of partial product signals which are needed are provided. The partial product signal generating circuits produce the partial product signals in accordance with the state of predetermined bits of a multiplier. Each partial product signal is added, thereby obtaining a multiplication output of the multiplicand. The pipeline processing is performed in the adding operation of each partial product signal. The multiplier and multiplicand are delayed. The predetermined partial product signal generating circuits are arranged immediately before the adders which need the partial product signals, thereby obtaining the partial product. With this digital multiplying circuit, the total number of bits of registers is reduced and the circuit scale is made small.

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Kanagawa, Japan

Seiichiro Iwase