Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Seiichiro Azuma

Hirotaka Nishizawa

Kazuo Tanaka

Toshio Yamada

Osamu Kasahara

Sinichi Suzuki

Mikinori Kawaji

Takayuki Yoshitake

Sinmei Hirano

Yasusi Sekine

Kazuaki Ootoshi

Masataka Miyama

Shuji Kawata

There is provided a semiconductor integrated circuit device having bipolar transistors each composed of an emitter region, base region, and collector region arranged vertically on a semiconductor substrate, said collector region having a plane figure, with the square corners thereof cut off. To be concrete, the buried collector region having a high concentration of impurity has its square corners cut off and the base region formed on the major surface of the epitaxial layer formed on said buried collector region has also its square corners cut off. The bipolar transistor having such a plane figure has a reduced parasitic capacity and an increased operating speed. A manufacturing method is also provided capable of producing a highly reliable groove isolation structure with a low dielectric constant.

Semiconductor integrated circuit device having an improved vertical

An isolation and flattening technique for a semiconductor substrate having active devices, such as a bipolar transistor, and a MISFET, formed thereon, is disclosed. The technique includes forming grooves, to the main surface of a non-active region of a semiconductor substrate or a semiconductor layer, each groove extending into the substrate or layer and forming island regions of the substrate or layer, forming a burying material and a first mask having an etching rate greater than that of the burying material successively over the entire surface of the semiconductor substrate or the semiconductor layer including areas on the upper surface of the island regions and in the grooves, such that the film thickness is made virtually uniform for each of the surfaces, forming a second mask on the surface of the first mask, through which the region on each of the island regions is exposed and in which the end of the opening is situated from the end of the island region to the outside of the island region within a distance 0.7 times of the film thickness for the sum of the burying material and the first mask, and applying isotropic etching successively to each of the first mask and the burying material by using the second mask as an etching mask, under a condition in which the etching rate for the first mask is greater than that for the burying material.

Method of manufacturing a semiconductor integrated circuit device

Growing community of inventors

Ohme, Japan

Seiichiro Azuma