Hitachi, Ltd.

Seiichi Yoshizumi

Toyohiko Kagimasa

Shizuo Gotou

Kikuo Takahashi

Yooichi Shintani

Yoshiki Matsuda

Yoshie Ono

An information processing system including a group of translation tables in a multilevel structure for achieving address translation from a virtual address into a real address, a control register for keeping a starting point address data of a translation table located at a highest level among the address translation tables and a level data indicating a level (n) of the translation table at the highest level among the group of translation tables, and a unit for sequentially accessing the address translation tables at levels lower than the level (n) indicated by the level data in the control register based on the starting point address data and a virtual address to be translated, thereby translating the virtual address into a real address.

Data processor having multilevel address translation tables

A data processor which specifies either of a predetermined maximum length of an adddress (a bits) and a length of an address less than the former length and at plural registers having a number of length of bits (r bits) of the maximum address length or greater. The data processor reads out lower-order d bits for data or r bits for an address of the one of the plural registers (7) specified by a first instruction to perform an arithmetic or logic operation, and writes the result into one of the plural registers. Moreover, the processor reads out bits having specified length of an address from the one of the plural registers specified in a second instruction to generate an a-bit address, and reads out d for data or r bits for an address from a main storage device (5) in response to the thus-generated address to write the d or r bits into one of the plural registers. Since the data length is consistently d bits irrespective of specified effective length of an address, direct data transfer is enabled between programs each having a different effective length of an address thereby facilitating extension of the length of a storage address and assuring compatibility with conventional data processors.

System for processing data with multiple virtual address and data word

A data processing apparatus for an address boundary check circuit employed in combination with a virtual storage comprises a segment table register provided in association with an address translation table for storing an area discriminating signal indicating whether data to be checked in respect to the address boundary is assigned to unit areas resulting from division of the virtual storage and holding a limit address signal indicating the extent of the area assigned to data which requires an address boundary check of a virtual address accessing the data when the data is found in that area, a register holding a virtual base address for storing a register discriminating signal indicating whether or not the base address is for data to be checked in respect to the address boundary, and an address boundary check circuitry for deciding on the basis of the aforementioned first to third signals whether or not a virtual address calculated in response to an instruction erroneously goes beyond the address boundary.

Data processing apparatus with a virtual storage address boundary check

A mode register stores a mode bit for each of the general registers, an access circuit accesses the general registers and the mode register so that a general register designated by an instruction and a corresponding mode bit are read out together. A data use circuit or a data supply circuit connected to the general registers includes a circuit portion which effectively changes the significant bit length of the data read out of the designated general register or of the data to be written into the designated general register.

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Hino, Japan

Seiichi Yoshizumi