Texas Instruments Corporation

Seiichi Yamamoto

Jimmie D Childers

Masanari Takeyasu

Yutaka Takahashi

Jim Childers

Takashi Inui

Tomohiro Suzuki

Peter Reinecke

Kiyoshi Nakatsuka

Atsushi Naito

A processor (10) comprises a plurality of processing elements each having an input register (11), first memory bank (12), first sense amplifier (40), ALU (13), output register (16), second memory bank (15) and second sense amplifier (42). The first sense amplifier (40) is shared between the input register (11) and first memory bank (12). The second sense amplifier (42) is shared between the output register (16) and second memory bank (15). The sense amplifier (40,42) may be paused to prevent voltage spikes during a read/write operation, or to wait until a calculation is completed.

Storage circuitry using sense amplifier shared between memories of

A processor (10) comprises a plurality of processing elements each having an input register (11), first memory bank (12), first sense amplifier (40), ALU (13), output register (16), second memory bank (15) and second sense amplifier (42). The first sense amplifier (40) is shared between the input register (11) and first memory bank (12). The second sense amplifier (42) is shared between the output register (16) and second memory bank (15). The sense amplifier (40,42) may be paused to prevent voltage spikes during a readrite operation, or to wait until a calculation is completed.

Storage circuit

Circuitry and method for performing a double instruction during a single clock cycle in a synchronous vector processor (SVP) device having a plurality of one-bit processor elements organized in a linear array. The circuitry includes four sense amps per processor element and one ALU to enable reading of four data bits per clock cycle. The method includes reading data from each register file in a processor element and writing the data in one of the register file memory banks; enabling a 2:1 reduction in the amount of required instructions and a substantial reduction in overall cycle time.

Circuitry and method for performing two operating instructions during a

Storage circuitry using sense amplifier with temporary pause for voltage

The present invention relates generally to single instruction, multiple data processors. More particularly, the invention relates to processors having a one dimensional array of processing elements, that finds particular application in digital signal processing such as Improved Definition Television (IDTV). Additionally, the invention relates to improvements to the processors, television and video systems and other systems improvements and methods of their operation and control.

Three transistor dual port dynamic random access memory gain cell

Data selector circuit including a plurality of data registers connected in parallel via corresponding output buffers to a plurality of output drivers, wherein a decoder and selector portion is interposed between the output buffers and the output drivers for selectively providing one of a plurality of serial data output sequences from the data registers to the output drivers rather than a parallel data output format from the plurality of data registers which would otherwise occur. The decoder and selector portion is controlled by a partial address buffer which is provided with serial sequence selection data. Upon decoding the serial sequence selection data of the partial address buffer, a plurality of MOS transistors included in the selector portion are rendered conductive in sequence in response to respective control signals applied to the gates thereof to connect the plurality of data registers via their output buffers to respective output drivers in a sequence determined by the decoded selection data of the partial address buffer for serial data output in the selected serial data output sequence.

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Ibaragi, Japan

Seiichi Yamamoto