Thine Electronics, Inc.

Seiichi Ozawa

Hironobu Akita

Satoshi Miura

Yohei Ishizone

Shuhei Yamamoto

Junichi Okamura

Jun-ichi Okamura

Reception devicestoare arranged one-dimensionally in this order. The reception devicehas a data input buffer, a first clock input buffer, and a first clock output buffer. The first clock input bufferbuffers a clock input to the first clock terminals Pand P, and outputs it to the first clock output buffer. The first clock output bufferbuffers a clock input from the first clock input bufferand outputs it from the second clock terminals Pand P. The data input terminals Pand Pare located between the first clock terminal and the second clock terminal.

Transmission device, reception device, transmission-reception system, and image display system

A video transmission devicehas: a packerwhich receives a video signal, a sync signal, and a data-enable signal, and generates a plurality of packet signals by packetizing the video signal and the sync signal based on the data-enable signal and according to the number of bytes of a packet corresponding to the number of gradation bits of the video signal; an encode unitwhich generates a plurality of encoded packet signals by encoding the plurality of packet signals; and a serializerwhich generates a serial packet signal by parallel-serial converting the plurality of encoded packet signals. The packergenerates a control signal including a pulse with a pulse width corresponding to the number of bytes of the packet, and the encode unitsubjects a portion of the packet signals corresponding to the pulse in the control signal from the packer, to an encode process which is different from a process for the other portion.

Video signal transmission device, video signal reception device, and video signal transmission system

The present invention provides a transmission apparatus and a reception apparatus easy to sample data correctly by a clock in the reception apparatus. In a detection sectionof a reception apparatus, based on data output from a sampler section, both or either of detection of a phase difference between data received by a data reception sectionand a clock received by a clock reception section, and/or waveform distortion of this data is performed. A detection signal indicating a result of detection by the detection sectionis transmitted to a transmission apparatusby a detection signal transmission section. In the transmission apparatus, by a control section, based on the detection signal received by a detection signal reception section, both or either of control of adjustment of a phase between data transmitted by a data transmission sectionand a clock transmitted by a clock transmission section, and/or adjustment of an amplitude of the data is performed.

Transmission apparatus, reception apparatus, transmission-reception system, and image display system

A data reception unitof a reception devicereceives calibration data to detect a data reception state or a clock reception state in the reception devicefrom a data transmission unitof a transmission device. A decoder unitcauses a transmission unitto send out calibration sample data that a sampler unitobtained by sampling calibration data to the transmission device. A control unitof the transmission devicedetects a data reception state or a clock reception state in the reception devicebased on calibration sample data received from the reception deviceand controls the data transmission unitand a clock transmission unitbased on the detection result.

Transmitting apparatus, receiving apparatus, transmitting/receiving system, and image display system

A clock data restoration device (A) includes a sampler portion (), a phase comparison portion (), a drive portion (), a charge pump (), a capacitive element (), a potential adjustment portion () and a voltage control oscillator (). The phase comparison portion () outputs a signal (UP) that becomes a significant value when the phase of a clock (CKX) delays with respect to an input digital signal, and outputs a signal (DN) that becomes a significant value when the phase advances. The drive portion () increases or decreases a value &#x3b4; to or from a variable &#x394; when the signals (UP) and (DN) become a significant value, and increases or decrease a value N to or from the variable &#x394; when the value of the variable &#x394; is equal to or more than +N or when the value of the variable &#x394; is equal to or less than &#x2212;N, and signals (UPFRQ) and (DNFRQ) are output to the charge pump (). The potential adjustment portion () increases or decreases a potential at a first end of a capacitive element () based on the signals (UP) and (DN).

Clock data restoration device

Provided are a transmission device, a receiving device, and a communication system having a simple configuration and capable of reliably executing the confirmation of a changed bit rate. The communication systemsends, to the receiving device, a serial data signal Sthat is set as a constant value across a period of a constant multiple of a cycle of the clock when a bit rate of a serial data signal Sin the transmission deviceis changed. The receiving devicethat received the serial data signal Sreceives training data Tfrom the transmission devicewhen it is determined that the serial data signal Sis a constant value across a period of a constant multiple of a cycle of the clock, and proceeds to the processing of confirming the changed bit rate.

Transmission device, receiving device and communication system

A clock data restoration device, which restores a clock signal and data on the basis of an inputted digital signal, comprises an equalizer, a sampler, a clock generator, an equalizer controller, and a phase monitor. A clock signal CK or CKX as a clock signal restored on the basis of the input digital signal is generated through loop processing by the samplerand the clock generator. The level adjustment amount of a high frequency component of the digital signal by the equalizeris controlled through loop processing by the equalizer, the samplerand the equalizer controller

A clock/data recovery devicecomprises a sampler, a detector, an offset determination part, a clock output part, and a DA converter. The phases of clock signals CK and CKX are adjusted so as to match with the phase of an input digital signal. An offset amount (&#xb1;Voff) added in the sampleris adjusted so as to match with a peak time of a data transition time distribution of a first signal in a case where a value D(n&#x2212;1) is HIGH level, and is adjusted so as to match with a peak time of a data transition time distribution of a second signal in a case where the value D(n&#x2212;1) is LOW level. Either of the clock signals CK and CKX is outputted as the recovered clock signal. Time series data of a digital value D(n) is outputted as the recovered data.

Clock data recovery device

With the clock data restoration device, as a result of the processing of a loop which comprises the sampler section, detection section, timing determination section, and clock output section, the respective phases of the clock signal CKXA, clock signal CKXB, and clock signal CK are adjusted to match the phase of the input digital signal, the digital signal sampling time indicated by the clock signal CKXA is adjusted to match the peak time of the distribution of data transition times in a case where the value D (n&#x2212;2) and value D(n&#x2212;1) of the preceding two bits differ from one another, and the digital signal sampling time indicated by the clock signal CKXB is adjusted to match the peak time of the distribution of data transition times in a case where the value D (n&#x2212;2) and value D(n&#x2212;1) of the preceding two bits are equal to one another.

The clock data restoration deviceis a device which restores a clock signal and data on the basis of an input digital signal and comprises an equalizer section, a sampler section, a clock generation section, an equalizer control section, and a phase monitor section. As a result of the loop processing of the equalizer section, the sampler section, and the equalizer control section, a control of a level adjustment amount of the digital signal by the equalizer sectionis carried out. However, the control is stopped by the phase monitor sectionwhen the phase difference between the clock signal CK and the digital signal is greater than a predetermined value. As a result, a clock signal and data can be restored more accurately.

Clock data restoring device

[Problems] To realize a reliable and stable transfer of digital data that does not require a reference clock and a handshake operation. [Means for Solving the Problem] The present invention provides a digital data transfer method for alternately and periodically transferring first information and second information respectively in a first period and in a second period, wherein: an amount of information of the first information per unit time in the first period is greater than an amount of information of the second information per unit time in the second period; and the second information in the first period is transferred as pulse-width-modulated serial data.

Transmitter circuit, receiver circuit, clock data recovery phase locked loop circuit, data transfer method and data transfer system

A semiconductor integrated circuit which transmits voice data as ancillary data while maintaining transmission quality without increasing the number of transmission cables in a system for carrying out serial transmission of image data as main data. The semiconductor integrated circuit includes a main data transmitting circuit for converting main data into serial data and transmitting the serial data via at least one transmission path in synchronization with a clock signal, and an ancillary data transmitting circuit for pulse-width-modulating the clock signal by using ancillary data to generate a modulated clock signal having at least three kinds of pulse widths in a predetermined order and transmitting the modulated clock signal via another transmission path.

Semiconductor integrated circuit and data transmission system

A phase-selective type frequency modulator capable of easing the restriction on a phase range of a modulated clock signal. The phase-selective type frequency modulator includes a multiphase clock signal generating circuitfor generating N-phase clock signals; a control circuitfor sequentially activating one of first group of clock selection signals indicating a clock signal to be selected from the N-phase clock signals; an edge appearance time adjustment circuitfor adjusting a rising edge appearance time and/or a trailing edge appearance time of the first group of clock selection signals outputted from the control circuitto output second group of clock selection signals; and a modulated clock signal generating circuitfor selecting one clock signal from the N-phase clock signals in accordance with an activated state of the second group of clock selection signals outputted from the edge appearance time adjustment circuitto output a modulated clock signal MCK.

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Wako, Japan

Seiichi Ozawa