Nec Corporation

Nippon Electric Co., Ltd.

Seiichi Noda

Makoto Yoshimoto

Eisaku Sasaki

Katsuhiro Nakamura

Yoichi Tan

Shinichi Koike

Masayoshi Watanabe

The present invention relates to a modulation and demodulation method of minimizing an error rate and applying it to a differential operation modulo 4. A modulation apparatus includes a Gray coding circuitto which data of (2+1) bits are inputted (where 'n' is an integer more than 1) and which encodes 2 bits of an input signal of (2+1) bits to a Gray code as a signal for allowing four quadrants to be identified, an encoding circuitthat encodes 3 bits of the input signal of (2+1) bits as a signal indicating any one of eight subgroups provided in each of the four quadrants so that an average Hamming distance between adjacent subgroups within its quadrant becomes a minimum, and a mapping circuitthat maps binary data encoded by the Gray coding circuitand the encoding circuiton the four quadrants.

Modulation and demodulation method, modulation apparatus and demodulation apparatus

A modulation and demodulation system capable of minimizing a bit error rate in a six-phase phase modulation method. A senary signal phase-modulated and outputted by a modulator is received and phase-modulated by a destination demodulator to a binary signal before conversion by the modulator. The modulator assigns (0, 0), (0, 1), (0, 2), (1, 2), (1, 1) and (1, 0) which are senary signals (b, t) to first to sixth phases respectively. The demodulator performs a conversion process from the senary signals to the binary signals, for instance, by storing transmitted senary signals and sequentially converting every senary signal of length m to binary signal of length b so as to output them. The process of the demodulator assigns the first to sixth phases as the senary signals (b, t) to (0, 0), (0, 1), (0, 2), (1, 2), (1, 1) and (1, 0) respectively.

Modulation and demodulation system, modulator, demodulator and phase modulation method and phase demodulation method used therefor

Disclosed is a method and a system for performing N-ary modulation in which bit errors may be reduced against symbol error. A binary signal, a bit length thereof being n, is associated with N-ary signals arranged in first and second phase planes respectively for transmission, wherein N is not a number belonging to powers of 2 but is a number belonging to a series beginning from 12 and sequentially doubled, that is, any one of 12, 24, 48, 96, . . . , and wherein n is such that, if the bit length n is 7, 9, 11, 13, . . . , the number N is 12, 24, 48, 96, . . . , respectively, two out of the n bits are allocated for identifying four quadrants of the first phase plane, two out of the remaining (n&#x2212;2) bits are allocated for identifying four quadrants of the second phase plane. The binary signal of three out of the n bits is converted into two digits of ternary signals (T, T). The ternary signals are mapped to the first and second phase planes with rotational symmetry of 90&#xb0; or with axial symmetry.

Multi-level modulation method and system

Disclosed is a CDMA communication system and method that make it possible to accommodate a greater number of user terminals that can be connected per facilities investment. Ternary phase-shift keying (TPSK) modulation is applied as primary modulation in a CDMA communication system. It is possible to deliver far performance in which the Eb/No ratio is improved by about 0.75 dB, in comparison with BPSK and QPSK modulation, in order to obtain the required signal quality. Accordingly, the number of user terminals that can be connected simultaneously in a CDMA system can be increased by about 19%.

Code division multiple access communication system and method

In a QAM modulation system, (3p+1) or (3p+2) input signal strings, where p is an integer not less than 3 or 2, are converted into three (p+1) string signals which are then allocated to three phase planes. The converted three (p+1) string signals are time-division multiplexed and multi-level modulated to realize QAM modulation in which the n-ary number may be set to approximately 2or 2. In a QAM modulation system, (4p+3) input signal strings, where p is an integer not less than 3, are converted into three (p+1) string signals, which are then allocated to three phase planes, time-division multiplexed and multi-level modulated to realize QAM modulation in which the n-ary number may be set to approximately 2.

Multi-level modulation apparatus, multi-level demodulation apparatus, multi-level modulation/demodulation communication system, program and modulation/demodulation method

A communication system for transmitting a six-phase modulated signal and including an efficient error correction system suitable for the six-phase modulated signal is disclosed. A transmitting apparatus comprises a ternary error correction encoding circuit for generating a ternary transmit sequence, a parity generation circuit for generating a parity, a parity insertion circuit for inserting the parity into a binary transmit sequence, and a six-phase modulator for performs six-phase modulation. A receiving apparatus comprises a parity generation circuit for generating a parity, a parity separation circuit for separating a received parity, a parity comparison circuit for calculating a difference between the parity and the received parity, a syndrome calculation circuit for calculating a syndrome, a ternary error correction decoding circuit for producing a ternary decoded sequence, a high-order digit correction circuit for producing a binary decoding sequence, and a 6-ary to binary conversion circuit for producing a binary received signal is obtained from the ternary decoded sequence and binary decoding sequence.

Multi-level communication system and method with error correction

A QAM modulation system capable of setting a number of multilevel to approximate 2(p is an integer equal to or more than 3) or 2. An input data signal of 4p+1 bits are converted into four signals of p+1 bits, there being a predetermined relationship between the input data signal and the converted signals. The converted four signals are assigned to four phase planes, respectively. The four signals are time-division multiplexed and multilevel-modulated. Thereby, it becomes possible to set the number of multilevel to approximate 2.

Modulation device, demodulation device, communication system using the same, program and method for implementing modulation and demodulation

In a phase modulation apparatus for modulating a phase of a carrier signal by an input signal to produce a phase-shift-keying-modulated wave, a data converter converts an input data signal having 3 bits long as the input signal into first and second ternary converted data signals. A ternary phase shift keying modulator modulates, in synchronism with a clock signal, the phase of the carrier signal by the first and the second ternary converted data signals to produce, as the phase-shift-keying-modulated wave, first and second ternary phase shift keying modulated signals, respectively. Disposed between the data converter and the ternary phase shift keying modulator, a parallel-serial converter temporally multiplexes the first and the second ternary converted data signals into first and second multiplexed signals, respectively. The parallel-serial converter supplies the ternary phase shift keying modulator with the first and the second multiplexed signals.

Phase shift keying modulation including a data converter for converting an input data signal having 3 bits long into two ternary converted data signals

A communication system comprises a transmitting apparatus and receiving apparatus for transmitting/receiving a N-ary signal, based on a prime number exceeding 2, inclusive of an efficient error correction system. The transmitting apparatus includes a binary to N-ary converting unit for converting a binary transmit signal into an N-ary signal, as an information sequence, where the N of the N-ary number is a prime number exceeding 2, an encoding unit for generating a transmit sequence, comprised of BCH code on a Galois field with the number of elements being a prime number exceeding 2, and a multi-level modulating unit for multi-level modulating the transmit sequence and for transmitting the multi-level modulated transmit sequence to a receiving apparatus. The receiving apparatus includes a demodulating unit for demodulating the received signal from the transmitting apparatus and for producing a multi-leveled received sequence, with the multi-level of the received sequence being a prime number exceeding 2, a decoding unit for decoding the received sequence by a decoding method for a BCH code on a Galois field with the number of elements being a prime number exceeding 2, and a N-ary to binary conversion unit for producing a decoded binary signal from the N-ary signal as a decoded sequence.

Communication system and method

In order to produce first and second Lee-error correcting code sequences in a multilevel quadrature amplitude modulator comprising a code converting unit (10) for converting first and second 2.sup.m -level input digital signals into first and second major converted signals by rearranging a square signal point arrangement into an approximately circular arrangement on a phase plane, each of the first and the second major converted signals consisting of m binary bits numbered from a first (least significant) bit through an m-th (most significant) bit, a first error correcting code producing circuit (21) carries out error correcting calculation for the first through an n-th bits of the first major converted signal to produce the first Lee-error correcting code sequence where n represents an integer which is not less than two and is not less than m. Similarly, a second error correcting code producing circuit (22) produces the second Lee-error correcting code sequence. The first and the second major converted signals are multiplexed with the first and the second error correcting code sequences into first and second major multiplexed signals, respectively. The first and the second major multiplexed signals are modulated into a multilevel quadrature amplitude modulated signal. In a counterpart multilevel quadrature amplitude demodulator, an inverse operation is carried out to produce the first and the second input digital signals.

Multilevel quadrature amplitude modulator capable of reducing a maximum

In an encoder for use in encoding each input signal unit of N bits into each of error correcting codewords, each input signal unit is grouped into a plurality of parts which have bit lengths N1 and N2 in consideration of a transmission rate on a transmission path and which are individually encoded into partial encoded codewords which individually include redundancy signals, respectively. The partial encoded codewords may have different error correction ability and different code lengths. The partial encoded codewords are combined together into each of the error correcting codeword which may be transmitted to the transmission path at a transmission rate close to an allowable transmission rate of the transmission path. A decoder decodes each error correcting codeword into each of output signal units by dividing each error correcting codeword into divided codewords and by individually decoding the divided codewords.

Error correcting system capable of effectively using an allowable

An equalizer is provided with a branching device for branching a digitally modulated signal into two outputs. A series of weighting devices weights one of the outputs of the branching means, and a series of second weighting devices equal to or fewer in number than the first weighting devices weights the remaining output of the branching means. Combining elements equal in number to the first weighting devices combine two or three inputs, and delaying means fewer in number than the combining elements are interconnected with the combining elements in a sequential, alternating manner. The outputs of the first weighting devices are respectively applied to the combining elements while those of the second weighting devices are respectively applied to selected ones of the combining elements. The invention provides a construction where the number of taps of the equalizer may be easily increased without creating the necessity of combining circuits having an increased number of inputs.

Transversal equalizer

In a multilevel modulator for use in modulating an input digital signal of N levels into a multilevel modulated signal, the input digital signal is converted by a code converting unit into a major converted signal for the input digital signal and a minor converted signal corresponding to the major converted signal. The major converted signal is rearranged into groups each of which consists of a predetermined number of levels smaller than N and which is produced in a time division fashion together with with minor converted signal. A signal producing unit processes each group to produce a Lee-error correcting code sequence. Alternatively, major and minor converted signals are produced on quadrature-phase amplitude modulation of a circular signal arrangement of N-levels to divide the circular signal arrangement into a square signal arrangement and the remaining signal arrangement. In a counterpart multilevel demodulator, an inverse operation is carried out to reproduce the input digital signal.

Multilevel modulator comprising a compact error correcting code

A digital signal combining circuit for a diversity receiver for digital communication comprises buffer memories (16) for memorizing digital signal sequences produced by receiver units (11, 12), respectively, and an APC loop (26-39) for locking the phases of read-out clocks for simultaneously reading the memories to an averaged phase of the digital signal sequences. No code error appears in an output signal of the receiver provided that the phase difference between two of the digital signal sequences from which the output signal is selected, is less than m bit periods, where m represents the number of memory cells of each buffer memory.

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Tokyo, Japan

Seiichi Noda