Kabushiki Kaisha Toshiba

Seiichi Nishio

Kimiyoshi Usami

Fumihiro Minami

Takeshi Kitahara

Naomi Takeda

Shozo Isobe

Masami Aihara

Yuichiro Matsuoka

A computer aided design technique for clock gated logic circuits effective to reduce the electric power consumption is disclosed. The computer aided design for clock gated logic circuits is conducted by extracting, by the use of information about a clock gated logic circuit under the design, a halt condition under which a clocked circuit driven by a clock signal can halt with no clock signal supplied, generating enable signal candidates, from a halt condition, which can be used as enable signals in the clock gated logic circuit, analyzing the clock gated logic circuit in order to obtain information about a delay time of signal transmission and electric power consumption reduction if respective one of enable signal candidates is used as an enable signal of a clock gating circuit inserted in the clock gated logic circuit under the design, storing enable signal candidate information including the result of the analysis conducted by an analysis step in an information store, selecting an appropriate one of the enable signal candidates which satisfy given restrictions regarding a delay time of signal transmission in the clock gated logic circuit under the design, by the use of enable signal candidate information; and adding the clock gating circuit activated with the enable signal as selected by enable signal selection step to the clock gated logic circuit under the design.

Clock supplying circuit and method having enable buffer cells with first and second input terminals

A circuit design support apparatus partially converts a description of a circuit model to simulate the circuit operation. A register signal replacement section replaces a register signal with a variable in a process related with the register signal of the description and inserts a declaration of the variable in the process instead of a declaration of the register signal in the description. A clock signal simplification section replaces a clock signal with a variable in a clock signal reference process of the description and unifies a clock signal update process to the clock signal reference process in the description.

Circuit design support apparatus and a method

A computer aided design technique for clock gated logic circuits effective to reduce the electric power consumption is disclosed. The computer aided design for clock gated logic circuits is conducted by extracting, by the use of information about a clock gated logic circuit under the design, a halt condition under which a clocked circuit driven by a clock signal can halt with no clock signal supplied, generating enable signal candidates, from said halt condition, which can be used as enable signals in the clock gated logic circuit, analyzing the clock gated logic circuit in order to obtain information about a delay time of signal transmission and electric power consumption reduction if respective one of enable signal candidates is used as an enable signal of a clock gating circuit inserted in the clock gated logic circuit under the design, storing enable signal candidate information including the result of the analysis conducted by said analysis step in a information store means, selecting an appropriate one of the enable signal candidates which satisfy given restrictions regarding a delay time of signal transmission in the clock gated logic circuit under the design, by the use of said enable signal candidate information; and adding the clock gating circuit activated with the enable signal as selected by said enable signal selection step to the clock gated logic circuit under the design.

Method and apparatus for clock gated logic circuits to reduce electric power consumption

In a logic circuit diagram processing apparatus, when an original signal name or an original signal line is designated, all the signal lines associated with the designated signal (i.e. signal lines through which the designated signal is passed; logic elements to which the designated signal lines are connected; signal lines connected to the logic elements to which already-traced signal lines are connected, etc.) are displayed in color or colors, for instance, visually different from that of other signal lines, for providing an easy operator's visual confirmation or visual check of a logic circuit.

Growing community of inventors

Kanagawa-ken, Japan

Seiichi Nishio